Fusion Family of Mixed Signal FPGAs
Revision 4 2-55
t
SUPGLOSSPRO
Page Loss Protect Setup Time for the Control Logic 1.69 1.93 2.27 ns
t
HDPGLOSSPRO
Page Loss Protect Hold Time for the Control Logic 0.00 0.00 0.00 ns
t
SUPGSTAT
Page Status Setup Time for the Control Logic 2.49 2.83 3.33 ns
t
HDPGSTAT
Page Status Hold Time for the Control Logic 0.00 0.00 0.00 ns
t
SUOVERWRPG
Over Write Page Setup Time for the Control Logic 1.88 2.14 2.52 ns
t
HDOVERWRPG
Over Write Page Hold Time for the Control Logic 0.00 0.00 0.00 ns
t
SULOCKREQUEST
Lock Request Setup Time for the Control Logic 0.87 0.99 1.16 ns
t
HDLOCKREQUEST
Lock Request Hold Time for the Control Logic 0.00 0.00 0.00 ns
t
RECARNVM
Reset Recovery Time 0.94 1.07 1.25 ns
t
REMARNVM
Reset Removal Time 0.00 0.00 0.00 ns
t
MPWARNVM
Asynchronous Reset Minimum Pulse Width for the
Control Logic
10.00 12.50 12.50 ns
t
MPWCLKNVM
Clock Minimum Pulse Width for the Control Logic 4.00 5.00 5.00 ns
t
FMAXCLKNVM
Maximum Frequency for Clock for the Control Logic – for
AFS1500/AFS600
80.00 80.00 80.00 MHz
Maximum Frequency for Clock for the Control Logic – for
AFS250/AFS090
100.00 80.00 80.00 MHz
Table 2-25 • Flash Memory Block Timing (continued)
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std.
Units