Device Architecture
2-42 Revision 4
Flash Memory Block Pin Names
Table 2-19 • Flash Memory Block Pin Names
Interface Name Width Direction Description
ADDR[17:0] 18 In Byte offset into the FB. Byte-based address.
AUXBLOCK 1 In When asserted, the page addressed is used to access the auxiliary
block within that page.
BUSY 1 Out When asserted, indicates that the FB is performing an operation.
CLK 1 In User interface clock. All operations and status are synchronous to the
rising edge of this clock.
DATAWIDTH[1:0] 2 In Data width
00 = 1 byte in RD/WD[7:0]
01 = 2 bytes in RD/WD[15:0]
1x = 4 bytes in RD/WD[31:0]
DISCARDPAGE 1 In When asserted, the contents of the Page Buffer are discarded so that
a new page write can be started.
ERASEPAGE 1 In When asserted, the address page is to be programmed with all zeros.
ERASEPAGE must transition synchronously with the rising edge of
CLK.
LOCKREQUEST 1 In When asserted, indicates to the JTAG controller that the FPGA
interface is accessing the FB.
OVERWRITEPAGE 1 In When asserted, the page addressed is overwritten with the contents of
the Page Buffer if the page is writable.
OVERWRITEPROTECT 1 In When asserted, all program operations will set the overwrite protect bit
of the page being programmed.
PAGESTATUS 1 In When asserted with REN, initiates a read page status operation.
PAGELOSSPROTECT 1 In When asserted, a modified Page Buffer must be programmed or
discarded before accessing a new page.
PIPE 1 In Adds a pipeline stage to the output for operation above 50 MHz.
PROGRAM 1 In When asserted, writes the contents of the Page Buffer into the FB
page addressed.
RD[31:0] 32 Out Read data; data will be valid from the first non-busy cycle (BUSY = 0)
after REN has been asserted.
READNEXT 1 In When asserted with REN, initiates a read-next operation.
REN 1 In When asserted, initiates a read operation.
RESET 1 In When asserted, resets the state of the FB (active low).
SPAREPAGE 1 In When asserted, the sector addressed is used to access the spare
page within that sector.