Fusion Family of Mixed Signal FPGAs
Revision 4 2-37
Voltage Regulator and Power System Monitor (VRPSM)
The VRPSM macro controls the power-up state of the FPGA. The power-up bar (PUB) pin can turn on
the voltage regulator when set to 0. TRST can enable the voltage regulator when deasserted, allowing
the FPGA to power-up when user want access to JTAG ports. The inputs VRINITSTATE and
RTCPSMMATCH come from the flash bits and RTC, and can also power up the FPGA.
Table 2-15 • Memory Map for RTC in ACM Register and Description
ACMADDR Register Name Description Use
Default
Value
0x40 COUNTER0 Counter bits 7:0 Used to preload the counter to
a specified start point.
0x00
0x41 COUNTER1 Counter bits 15:8 0x00
0x42 COUNTER2 Counter bits 23:16 0x00
0x43 COUNTER3 Counter bits 31:24 0x00
0x44 COUNTER4 Counter bits 39:32 0x00
0x48 MATCHREG0 Match register bits 7:0 The RTC comparison bits 0x00
0x49 MATCHREG1 Match register bits 15:8 0x00
0x4A MATCHREG2 Match register bits 23:16 0x00
0x4B MATCHREG3 Match register bits 31:24 0x00
0x4C MATCHREG4 Match register bits 39:32 0x00
0x50 MATCHBIT0 Individual match bits 7:0 The output of the XNOR gates
0 – Not matched
1 – Matched
0x00
0x51 MATCHBIT1 Individual match bits 15:8 0x00
0x52 MATCHBIT2 Individual match bits 23:16 0x00
0x53 MATCHBIT3 Individual match bits 31:24 0x00
0x54 MATCHBIT4 Individual match bits 29:32 0x00
0x58 CTRL_STAT Control (write/read) / Status
(read only) register bits
Refer to Table 2-16 on
page 2-36 for details.
0x00
Note: *Signals are hardwired internally and do not exist in the macro core.
Figure 2-30 • VRPSM Macro
VRPU
PUB
VRINITSTATE
RTCPSMMATCH
FPGAGOOD
PUCORE
VREN*
VRPSM
TRST*