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AFS1500-2FGG256PP

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型号: AFS1500-2FGG256PP
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  • AFS1500-2FGG256PP PDF文件
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功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AFS1500-2FGG256PP
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120%
Device Architecture
2-34 Revision 4
Modes of Operation
Standby Mode
Standby mode allows periodic power-up and power-down of the FPGA fabric. In standby mode, the real-
time counter and crystal block are ON. The FPGA is not powered by disabling the 1.5 V voltage
regulator. The 1.5 V voltage regulator can be enabled when the preset count is matched. Refer to the
"Real-Time Counter (part of AB macro)" section for details. To enter standby mode, the RTC must be first
configured and enabled. Then VRPSM is shut off by deasserting the VRPU signal. The 1.5 V voltage
regulator is then disabled, and shuts off the 1.5 V output.
Sleep Mode
In sleep mode, the real-time counter and crystal blocks are OFF. The 1.5 V voltage regulator inside the
VRPSM can only be enabled by the PUB or TRST pin. Refer to the "Voltage Regulator and Power
System Monitor (VRPSM)" section on page 2-37 for details on power-up and power-down of the 1.5 V
voltage regulator.
Standby and Sleep Mode Circuit Implementation
For extra power savings, VJTAG and VPUMP should be at the same voltage as VCC, floated or ground,
during standby and sleep modes. Note that when VJTAG is not powered, the 1.5 V voltage regulator
cannot be enabled through TRST.
VPUMP and VJTAG can be controlled through an external switch. Microsemi recommends ADG839,
ADG849, or ADG841 as possible switches. Figure 2-28 shows the implementation for controlling
VPUMP. The IN signal of the switch can be connected to PTBASE of the Fusion device. VJTAG can be
controlled in same manner.
Figure 2-28 • Implementation to Control VPUMP
PTBASE
PTEM
External
Pass
Transistor
2N2222
3.3 V
1.5 V
VPUMP (or JTAG)
Pin of Fusion
VPUMP (or JTAG) Supply
Fusion
ADG841
S
IN
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