Fusion Family of Mixed Signal FPGAs
Revision 4 5-13
Advance v0.8
(continued)
The voltage range in the "VPUMP Programming Supply Voltage" section was
updated. The parenthetical reference to "pulled up" was removed from the
statement, "VPUMP
can be left floating or can be tied (pulled up) to any voltage
between 0 V and 3.6 V."
2-225
The "ATRTNx Temperature Monitor Return" section was updated with information
about grounding and floating the pin.
2-226
The following text was deleted from the "VREF I/O Voltage Reference" section: (all
digital I/O).
2-225
The "NCAP Negative Capacitor" section and "PCAP Positive Capacitor" section
were updated to include information about the type of capacitor that is required to
connect the two.
2-228
1 µF was changed to 100 pF in the "XTAL1 Crystal Oscillator Circuit Input". 2-228
The "Programming" section was updated to include information about V
CCOSC
. 2-229
The VMV pins have now been tied internally with the V
CCI
pins. N/A
The AFS090"108-Pin QFN" table was updated. 3-2
The AFS090 and AFS250 devices were updated in the "108-Pin QFN" table. 3-2
The AFS250 device was updated in the "208-Pin PQFP" table. 3-8
The AFS600 device was updated in the "208-Pin PQFP" table. 3-8
The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the "256-Pin
FBGA" table.
3-12
The AFS600 and AFS1500 devices were updated in the "484-Pin FBGA" table. 3-20
Advance v0.7
(January 2007)
The AFS600 device was updated in the "676-Pin FBGA" table. 3-28
The AFS1500 digital I/O count was updated in the "Fusion Family" table. I
The AFS1500 digital I/O count was updated in the "Package I/Os: Single-/Double-
Ended (Analog)" table.
II
Advance v0.6
(October 2006)
The second paragraph of the "PLL Macro" section was updated to include
information about POWERDOWN.
2-30
The description for bit 0 was updated in Table 2-17 · RTC Control/Status Register. 2-38
3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section. 2-40.
All function descriptions in Table 2-18 · Signals for VRPSM Macro. 2-42
In Table 2-19 • Flash Memory Block Pin Names, the RD[31:0] description was
updated.
2-43
The "RESET" section was updated. 2-61
The "RESET" section was updated. 2-64
Table 2-35 • FIFO was updated. 2-79
The VAREF function description was updated in Table 2-36 • Analog Block Pin
Description.
2-82
The "Voltage Monitor" section was updated to include information about low power
mode and sleep mode.
2-86
The text in the "Current Monitor" section was changed from 2 mV to 1 mV. 2-90
The "Gate Driver" section was updated to include information about forcing 1 V on
the drain.
2-94
Revision Changes Page
