Fusion Family of Mixed Signal FPGAs
Revision 4 5-9
Advance v1.0
(January 2008)
All Timing Characteristics tables were updated. For the Differential I/O Standards,
the Standard I/O support tables are new.
N/A
Table 2-3 • Array Coordinates was updated to change the max x and y values 2-9
Table 2-12 • Fusion CCC/PLL Specification was updated. 2-31
A note was added to Table 2-16 · RTC ACM Memory Map. 2-37
A reference to the Peripheral’s User’s Guide was added to the "Voltage Regulator
Power Supply Monitor (VRPSM)" section.
2-42
In Table 2-25 • Flash Memory Block Timing, the commercial conditions were
updated.
2-55
In Table 2-26 • FlashROM Access Time, the commercial conditions were missing
and have been added below the title of the table.
2-58
In Table 2-36 • Analog Block Pin Description, the function description was updated
for the ADCRESET.
2-82
In the "Voltage Monitor" section, the following sentence originally had ± 10% and it
was changed to +10%.
The Analog Quad inputs are tolerant up to 12 V + 10%.
In addition, this statement was deleted from the datasheet:
Each I/O will draw power when connected to power (3 mA at 3 V).
2-86
The "Terminology" section is new. 2-88
The "Current Monitor" section was significantly updated. Figure 2-72 • Timing
Diagram for Current Monitor Strobe to Figure 2-74 • Negative Current Monitor and
Table 2-37 • Recommended Resistor for Different Current Range Measurement are
new.
2-90
The "ADC Description" section was updated to add the "Terminology" section. 2-93
In the "Gate Driver" section, 25 mA was changed to 20 mA and 1.5 MHz was
changed to 1.3 MHz. In addition, the following sentence was deleted:
The maximum AG pad switching frequency is 1.25 MHz.
2-94
The "Temperature Monitor" section was updated to rewrite most of the text and add
Figure 2-78, Figure 2-79, and Table 2-38 • Temperature Data Format.
2-96
In Table 2-38 • Temperature Data Format, the temperature K column was changed
for 85°C from 538 to 358.
2-98
In Table 2-45 • ADC Interface Timing, "Typical-Case" was changed to "Worst-Case." 2-110
The "ADC Interface Timing" section is new. 2-110
Table 2-46 • Analog Channel Specifications was updated. 2-118
The "V
CC15A
Analog Power Supply (1.5 V)" section was updated. 2-224
The "V
CCPLA/B
PLL Supply Voltage" section is new. 2-225
In "V
CCNVM
Flash Memory Block Power Supply (1.5 V)" section, supply was
changed to supply input.
2-224
The "V
CCPLA/B
PLL Supply Voltage" pin description was updated to include the
following statement:
Actel recommends tying VCCPLX to VCC and using proper filtering circuits to
decouple V
CC
noise from PLL.
2-225
The "V
COMPLA/B
Ground for West and East PLL" section was updated. 2-225
Revision Changes Page