Fusion Family of Mixed Signal FPGAs
Revision 4 5-3
Revision 2
(continued)
VPUMP was incorrectly represented as VPP in several places. This was corrected to
VPUMP in the "Standby and Sleep Mode Circuit Implementation" section and
Table 3-8 • AFS1500 Quiescent Supply Current Characteristics through Table 3-11 •
AFS090 Quiescent Supply Current Characteristics (21963).
2-34, 3-10
Additional information was added to the Flash Memory Block "Write Operation"
section, including an explanation of the fact that a copy-page operation takes no less
than 55 cycles (SAR 26338).
2-47
The "FlashROM" section was revised to refer to Figure 2-46 • FlashROM Timing
Diagram and Table 2-26 • FlashROM Access Time rather than stating 20 MHz as the
maximum FlashROM access clock and 10 ns as the time interval for D0 to become
valid or invalid (SAR 22105).
2-56, 2-57
The following figures were deleted (SAR 29991). Reference was made to a new
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGA
s, which covers these cases in detail (SAR 34862).
Figure 2-55 • Write Access after Write onto Same Address
Figure 2-56 • Read Access after Write onto Same Address
Figure 2-57 • Write Access after Read onto Same Address
The port names in the SRAM "Timing Waveforms", "Timing Characteristics", SRAM
tables, Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18., and
the FIFO "Timing Characteristics" tables were revised to ensure consistency with the
software names (SAR 35753).
2-66,
2-69,
2-68, 2-78
In several places throughout the datasheet, GNDREF was corrected to
ADCGNDREF (SAR 20783):
Figure 2-64 • Analog Block Macro
Table 2-36 • Analog Block Pin Description
"ADC Operation" section
2-80
2-81
2-107
The following note was added below Figure 2-78 • Timing Diagram for the
Temperature Monitor Strobe Signal:
When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad
drive strength ceases and becomes a 1 µA sink into the Fusion device. (SAR
24796).
2-96
The "Analog-to-Digital Converter Block" section was extensively revised,
reorganizing the information and adding the "ADC Theory of Operation" section and
"Acquisition Time or Sample Time Control" section. The "ADC Example" section was
reworked and corrected (SAR 20577).
2-99
Table 2-49 • Analog Channel Specifications was modified to include calibrated and
uncalibrated values for offset (AFS090 and AFS250) for the external and internal
temperature monitors. The "Offset" section was revised accordingly and now
references Table 2-49 • Analog Channel Specifications (SARs 22647, 27015).
2-98,
2-120
The "Intra-Conversion" section and "Injected Conversion" section had definitions
incorrectly interchanged and have been corrected. Figure 2-92 • Intra-Conversion
Timing Diagram and Figure 2-93 • Injected Conversion Timing Diagram were also
incorrectly interchanged and have been replaced correctly. Reference in the figure
notes to EQ 10 has been corrected to EQ 23 (SAR 20547).
2-112,
2-115,
2-116
The prescalar range for the 'Analog Input (direct input to ADC)" configurations was
removed as inapplicable for direct inputs. The input resistance for direct inputs is
covered in Table 2-50 • ADC Characteristics in Direct Input Mode (SAR 31201).
2-123
Revision Changes Page
