DC and Power Characteristics
3-24 Revision 4
Methodology
Total Power Consumption—P
TOTAL
Operating Mode, Standby Mode, and Sleep Mode
P
TOTAL
= P
STAT
+ P
DYN
P
STAT
is the total static power consumption.
P
DYN
is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
Operating Mode
P
STAT
= PDC1 + (N
NVM-BLOCKS
* PDC4) + PDC5+ (N
QUADS
* PDC6) + (N
INPUTS
* PDC7) +
(N
OUTPUTS
* PDC8) + (N
PLLS
* PDC9)
N
NVM-BLOCKS
is the number of NVM blocks available in the device.
N
QUADS
is the number of Analog Quads used in the design.
N
INPUTS
is the number of I/O input buffers used in the design.
N
OUTPUTS
is the number of I/O output buffers used in the design.
N
PLLS
is the number of PLLs available in the device.
Standby Mode
P
STAT
= PDC2
Sleep Mode
P
STAT
= PDC3
Total Dynamic Power Consumption—P
DYN
Operating Mode
P
DYN
= P
CLOCK
+ P
S-CELL
+ P
C-CELL
+ P
NET
+ P
INPUTS
+ P
OUTPUTS
+ P
MEMORY
+ P
PLL
+ P
NVM
+
P
XTL-OSC
+ P
RC-OSC
+ P
AB
Standby Mode
P
DYN
= P
XTL-OSC
Sleep Mode
P
DYN
= 0 W
Global Clock Dynamic Contribution—P
CLOCK
Operating Mode
P
CLOCK
= (PAC1 + N
SPINE
* PAC2 + N
ROW
* PAC3 + N
S-CELL
* PAC4) * F
CLK
N
SPINE
is the number of global spines used in the user design—guidelines are provided in the
"
Spine Architecture" section of the Global Resources chapter in the Fusion and Extended
Temperature Fusion FPGA Fabric User's Guide.
N
ROW
is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the Fusion and Extended Temperature
Fusion FPGA Fabric User's Guide.
F
CLK
is the global clock signal frequency.
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
Standby Mode and Sleep Mode
P
CLOCK
= 0 W
Sequential Cells Dynamic Contribution—P
S-CELL
Operating Mode
