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AFS1500-2FGG256PP

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型号: AFS1500-2FGG256PP
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  • AFS1500-2FGG256PP PDF文件
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功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AFS1500-2FGG256PP
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Fusion Family of Mixed Signal FPGAs
Revision 4 3-23
Static Power Consumption of Various Internal Resources
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
The number of NVM blocks used in the design
The number of Analog Quads used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-16 on
page 3-27.
Enable rates of output buffers—guidelines are provided for typical applications in Table 3-17 on
page 3-27.
Read rate and write rate to the RAM—guidelines are provided for typical applications in
Table 3-17 on page 3-27.
Read rate to the NVM blocks
The calculation should be repeated for each clock domain defined in the design.
Table 3-15 • Different Components Contributing to the Static Power Consumption in Fusion Devices
Parameter Definition
Power
Supply
Device-Specific Static Contributions
UnitsAFS1500 AFS600 AFS250 AFS090
PDC1 Core static power contribution in
operating mode
VCC 1.5 V 18 7.5 4.50 3.00 mW
PDC2 Device static power contribution in
standby mode
VCC33A 3.3 V 0.66 mW
PDC3 Device static power contribution in
sleep mode
VCC33A 3.3 V 0.03 mW
PDC4 NVM static power contribution VCC 1.5 V 1.19 mW
PDC5 Analog Block static power
contribution of ADC
VCC33A 3.3 V 8.25 mW
PDC6 Analog Block static power
contribution per Quad
VCC33A 3.3 V 3.3 mW
PDC7 Static contribution per input pin –
standard dependent contribution
VCCI See Table 3-12 on page 3-18
PDC8 Static contribution per input pin –
standard dependent contribution
VCCI See Table 3-13 on page 3-20
PDC9 Static contribution for PLL VCC 1.5 V 2.55 mW
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