Fusion Family of Mixed Signal FPGAs
Revision 4 3-21
Differential
LVDS – 2.5 7.74 88.92
LVPECL – 3.3 19.54 166.52
Applicable to Standard I/O Banks
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08
2.5 V LVCMOS 35 2.5 – 247.36
1.8 V LVCMOS 35 1.8 – 128.46
1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46
Table 3-13 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings
1
(continued)
C
LOAD
(pF) VCCI (V)
Static Power
PDC8
(mW)
2
Dynamic Power
PAC10 (µW/MHz)
3
Notes:
1. Dynamic power consumption is given for standard load and software-default drive strength and output slew.
2. PDC8 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.