Device Architecture
2-232 Revision 4
ISP
Fusion devices support IEEE 1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during
programming. In addition, programming via a microcontroller in a target system can be achieved. Refer to
the standard or the "In-System Programming (ISP) of Microsemi's Low Power Flash Devices Using
FlashPro4/3/3X" chapter of the Fusion FPGA Fabric User’s Guide for more details.
JTAG IEEE 1532
Programming with IEEE 1532
Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a
Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping
the global IO_EN signal deactivated, which also has the effect of disabling the input buffers.
Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this
unprogrammed state—different behavior from that of the ProASIC
PLUS®
device family. This is done
because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input
buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a
noninvasive instruction. Refer to the standard or the "In-System Programming (ISP) of Microsemi's Low
Power Flash Devices Using FlashPro4/3/3X" chapter of the Fusion FPGA Fabric User’s Guide for more
details.
Boundary Scan
Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and
the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is
composed of the test access port (TAP) controller, test data registers, and instruction register (Figure 2-
146 on page 2-233). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-185 on page 2-233).
Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),
TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI,
and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied
to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on
page 2-229 for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state
machine (16 states) that operates as shown in Figure 2-146 on page 2-233. The 1s and 0s represent the
values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and
DR indicate that the instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain High for
five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-
Logic-Reset state.
Fusion devices support three types of test data registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test data path. The 32-bit device identification register
is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register
observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells,
each with a serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the boundary scan register cells in a device into a
boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are
Table 2-184 • TRST and TCK Pull-Down Recommendations
VJTAG Tie-Off Resistance*
VJTAG at 3.3 V 200 to 1 k
VJTAG at 2.5 V 200 to 1 k
VJTAG at 1.8 V 500 to 1 k
VJTAG at 1.5 V 500 to 1 k
Note: *Equivalent parallel resistance if more than one device is on JTAG chain.
