Fusion Family of Mixed Signal FPGAs
Revision 4 2-221
Output Enable Register
Timing Characteristics
Figure 2-141 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
t
OESUE
50%
50%
t
OESUD
t
OEHD
50% 50%
t
OECLKQ
1
0
t
OEHE
t
OERECPRE
t
OEREMPRE
t
OERECCLR
t
OEREMCLR
t
OEWCLR
t
OEWPRE
t
OEPRE2Q
t
OECLR2Q
t
OECKMPWH
t
OECKMPWL
50% 50%
50% 50% 50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
Table 2-178 • Output Enable Register Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
OECLKQ
Clock-to-Q of the Output Enable Register 0.44 0.51 0.59 ns
t
OESUD
Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns
t
OEHD
Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns
t
OESUE
Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 ns
t
OEHE
Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 ns
t
OECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns
t
OEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns
t
OEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns
t
OERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns
t
OEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns
t
OERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns
t
OEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable
Register
0.22 0.25 0.30 ns
t
OEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable
Register
0.22 0.25 0.30 ns
t
OECKMPWH
Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.41 0.48 ns
t
OECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register 0.32 0.37 0.43 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.