Fusion Family of Mixed Signal FPGAs
Revision 4 2-217
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Figure 2-138 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Core
Array
Data Input I/O Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Enable
CLK
Pad Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
INBUF
TRIBUF
INBUF
INBUF
CLKBUF
INBUF