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AFS1500-2FGG256PP

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型号: AFS1500-2FGG256PP
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  • AFS1500-2FGG256PP PDF文件
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功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AFS1500-2FGG256PP
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120%
Device Architecture
2-208 Revision 4
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-156 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL
1
IIH
2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmAmA
Max.
mA
3
Max.
mA
3
µA
4
µA
4
15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 87 83 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Figure 2-130 • AC Loading
Table 2-157 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C
LOAD
(pF)
VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
Test Point
30 pF
50
25
SSTL2
Class I
VTT
Table 2-158 • SSTL 2 Class I
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
t
ZLS
t
ZHS
Units
Std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns
–1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns
–2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
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