Fusion Family of Mixed Signal FPGAs
Revision 4 2-207
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output
buffer.
Timing Characteristics
Table 2-153 • Minimum and Maximum DC Input and Output Levels
HSTL Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL
1
IIH
2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmAmA
Max.
mA
3
Max.
mA
3
µA
4
µA
4
15 mA
3
–0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15 55 66 10 10
Note:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Output drive strength is below JEDEC specification.
Figure 2-129 • AC Loading
Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C
LOAD
(pF)
VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
Test Point
20 pF
25
HSTL
Class II
VTT
Table 2-155 • HSTL Class II
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
t
ZLS
t
ZHS
Units
Std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns
–1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns
–2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.