Device Architecture
2-166 Revision 4
Figure 2-118 • Tristate Output Buffer Timing Model and Delays (example)
D
CLK
Q
D
CLK
Q
10% VCCI
t
ZL
V
trip
50%
t
HZ
90% VCCI
t
ZH
V
trip
50%
50%
t
LZ
50%
EOUT
PAD
D
E
50%
t
EOUT (R)
50%
t
EOUT (F)
PAD
DOUT
EOUT
D
I/O Interface
E
t
EOUT
t
ZLS
V
trip
50%
t
ZHS
V
trip
50%
EOUT
PAD
D
E
50%
50%
t
EOUT (R)
t
EOUT (F)
50%
VCC
VCC
VCC
VCCI
VCC
VCC
VCC
VOH
VOL
VOL
t
ZL
, t
ZH
, t
HZ
, t
LZ
, t
ZLS
, t
ZHS
t
EOUT
= MAX(t
EOUT
(R). t
EOUT
(F))