Device Architecture
2-164 Revision 4
Figure 2-116 • Input Buffer Timing Model and Delays (example)
t
PY
= MAX(t
PY
(R), t
PY
(F))
t
PYs
= MAX(t
PYS
(R), t
PYS
(F))
t
DIN
= MAX(t
DIN
(R), t
DIN
(F))
t
PY
(R)
PAD
Y
V
trip
GND
t
PY
(F)
V
trip
50%
50%
VIH
VCC
VIL
t
PYS
(R)
t
PYS
(F)
t
DIN
(R)
DIN
GND
t
DIN
(F)
50%50%
VCC
PAD
Y
t
PY
t
PYS
D
CLK
Q
I/O interface
DIN
t
DIN
To Array