Device Architecture
2-152 Revision 4
Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Figure 2-107 • Block Diagram of Output Enable Path
Figure 2-108 • Timing Diagram (option1: bypasses skew circuit)
Figure 2-109 • Timing Diagram (option 2: enables skew circuit)
ENABLE (OUT)
Skew Circuit
Output Enable
(from FPGA core)
I/O Output
Buffers
ENABLE (IN)
MUX
Skew Select
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns