Device Architecture
2-146 Revision 4
Electrostatic Discharge (ESD) Protection
Fusion devices are tested per JEDEC Standard JESD22-A114-B.
Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all
device pads against damage from ESD as well as from excessive voltage transients.
Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P side connected to GND and its N side
connected to the pad. During operation, these diodes are normally biased in the Off state, except when
transient voltage is significantly above VCCI or below GND levels.
By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Ta b le 2 -7 5 and
Table 2-76 on page 2-146 for more information about I/O standards and the clamp diode.
The second diode is always connected to the pad, regardless of the I/O configuration selected.
Table 2-75 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities
I/O Assignment
Clamp Diode Hot Insertion 5 V Input Tolerance
1
Input
Buffer
Output
Buffer
Standard
I/O
Advanced
I/O
Standard
I/O
Advanced
I/O
Standard
I/O
Advanced
I/O
3.3 V LVTTL/LVCMOS No Yes Yes No Yes
1
Yes
1
Enabled/Disabled
3.3 V PCI, 3.3 V PCI-X N/A Yes N/A No N/A Yes
1
Enabled/Disabled
LVCMOS 2.5 V No Yes Yes No No No Enabled/Disabled
LVCMOS 2.5 V / 5.0 V N/A Yes N/A No N/A Yes
2
Enabled/Disabled
LVCMOS 1.8 V No Yes Yes No No No Enabled/Disabled
LVCMOS 1.5 V No Yes Yes No No No Enabled/Disabled
Differential,
LVDS/BLVDS/M-
LVDS/ LVPECL
3
N/A Yes N/A No N/A No Enabled/Disabled
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.
Table 2-76 • Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities
I/O Assignment
Clamp
Diode
Hot
Insertion
5 V Input
Tolerance Input Buffer Output Buffer
3.3 V LVTTL/LVCMOS No Yes Yes
1
Enabled/Disabled
3.3 V PCI, 3.3 V PCI-X Yes No Yes
1
Enabled/Disabled
LVCMOS 2.5 V
3
No Yes No Enabled/Disabled
LVCMOS 2.5 V / 5.0 V
3
Yes No Yes
2
Enabled/Disabled
LVCMOS 1.8 V No Yes No Enabled/Disabled
LVCMOS 1.5 V No Yes No Enabled/Disabled
Voltage-Referenced Input Buffer No Yes No Enabled/Disabled
Differential, LVDS/BLVDS/M-LVDS/LVPECL
4
No Yes No Enabled/Disabled
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. In the SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide, select the
LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O
standard.
4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.
