Device Architecture
2-130 Revision 4
ACM Characteristics
1
74 MATCHREG2 Match register bits 23:16 RTC
75 MATCHREG3 Match register bits 31:24 RTC
76 MATCHREG4 Match register bits 39:32 RTC
80 MATCHBITS0 Individual match bits 7:0 RTC
81 MATCHBITS1 Individual match bits 15:8 RTC
82 MATCHBITS2 Individual match bits 23:16 RTC
83 MATCHBITS3 Individual match bits 31:24 RTC
84 MATCHBITS4 Individual match bits 39:32 RTC
88 CTRL_STAT Control (write) / Status (read) register
bits 7:0
RTC
Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC.
1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and
aq_wen signals have no impact.
Table 2-54 • ACM Address Decode Table for Analog Quad (continued)
ACMADDR [7:0] in
Decimal Name Description
Associated
Peripheral
Figure 2-97 • ACM Write Waveform
Figure 2-98 • ACM Read Waveform
D1
A1
t
SUEACM
t
HEACM
t
SUDACM
t
HDACM
t
SUAACM
t
HAACM
A0
D0
ACMCLK
ACMWEN
ACMWDATA
ACMADDRESS
A0 A1
RD0 RD1
t
MPWCLKACM
t
CLKQACM
ACMCLK
ACMADDRESS
ACMRDATA