Fusion Family of Mixed Signal FPGAs
Revision 4 2-127
Examples
Calculating Accuracy for an Uncalibrated Analog Channel
Formula
For a given prescaler range, EQ 30 gives the output voltage.
Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain)
EQ 30
where
Channel Output offset in V = Channel Input offset in LSBs x Equivalent voltage per LSB
Channel Gain Factor = 1+ (% Channel Gain / 100)
Example
Input Voltage = 5 V
Chosen Prescaler range = 8 V range
Refer to Table 2-51 on page 2-125.
Max. Output Voltage = (Max Positive input offset) + (Input Voltage x Max Positive Channel Gain)
Max. Positive input offset = (21 LSB) x (8 mV per LSB in 10-bit mode)
Max. Positive input offset = 166 mV
Max. Positive Gain Error = +3%
Max. Positive Channel Gain = 1 + (+3% / 100)
Max. Positive Channel Gain = 1.03
Max. Output Voltage = (166 mV) + (5 V x 1.03)
Max. Output Voltage = 5.316 V
Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages
Typical Conditions, T
A
= 25°C
Input Voltage
(V)
Calibrated Typical Error per Positive Prescaler Setting
1
(%FSR)
Direct ADC
2,3
(%FSR)
16 V (AT)
16 V (12 V)
(AV/AC)
8 V
(AV/AC) 4 V (AT)
4 V
(AV/AC)
2 V
(AV/AC)
1 V
(AV/AC) VAREF = 2.56 V
15 1
14 1
12 1 1
5221
3.3 2 2 1 1 1
2.5 3 2 1 1 1 1
1.8 4 4 1 1 1 1
1
1.5 5 5 2 2 2 1
1
1.2 7 6 2 2 2 1
1
0.9 9 9 4 3 3 1 1 1
Notes:
1. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the
"Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s Guide.
2. Direct ADC mode using an external VAREF of 2.56V±4.6mV, without Analog Calibration macro.
3. For input greater than 2.56 V, the ADC output will saturate. A higher VAREF or prescaler usage is recommended.
