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AFS1500-2FGG256PP

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型号: AFS1500-2FGG256PP
PDF文件:
  • AFS1500-2FGG256PP PDF文件
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功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AFS1500-2FGG256PP
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120%
Fusion Family of Mixed Signal FPGAs
Revision 4 2-121
Temperature Monitor Using Analog Pad AT
External
Temperature
Monitor
(external diode
2N3904,
T
J
= 25°C)
4
Resolution 8-bit ADC 4 °C
10-bit ADC 1 °C
12-bit ADC 0.25 °C
Systematic Offset
5
AFS090 uncalibrated
7
C
AFS090, AFS250, calibrated
7
C
AFS250, AFS600, AFS1500,
uncalibrated
7
11 °C
AFS600, AFS1500, calibrated
7
C
Accuracy ±3 ±5 °C
External Sensor Source
Current
High level, TMSTBx = 0 10 µA
Low level, TMSTBx = 1 100 µA
Max Capacitance on AT
pad
1.3 nF
Internal
Temperature
Monitor
Resolution 8-bit ADC 4 °C
10-bit ADC 1 °C
12-bit ADC 0.25 °C
Systematic Offset
5
AFS090 uncalibrated
7
C
AFS090, AFS250, calibrated
7
C
AFS250, AFS600, AFS1500
uncalibrated
7
11 °C
AFS600, AFS1500 calibrated
7
C
Accuracy ±3 ±5 °C
t
TMSHI
Strobe High time 10 105 µs
t
TMSLO
Strobe Low time 5 µs
t
TMSSET
Settling time 5 µs
Table 2-49 • Analog Channel Specifications (continued)
Commercial Temperature Range Conditions, T
J
= 85°C (unless noted otherwise),
Typical: VCC33A = 3.3 V, VCC = 1.5 V
Parameter Description Condition Min. Typ. Max. Units
Notes:
1. VRSM is the maximum voltage drop across the current sense resistor.
2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no
reliability concern on digital inputs as long as VIND does not exceed these limits.
3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.
4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance
allowed across the AT pins is 500 pF.
5. The temperature offset is a fixed positive value.
6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on
voltage on the pad.
7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer
to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s
Guide.
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