Fusion Family of Mixed Signal FPGAs
Revision 4 2-117
ADC Interface Timing
Table 2-48 • ADC Interface Timing
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
SUMODE
Mode Pin Setup Time 0.56 0.64 0.75 ns
t
HDMODE
Mode Pin Hold Time 0.26 0.29 0.34 ns
t
SUTVC
Clock Divide Control (TVC) Setup Time 0.68 0.77 0.90 ns
t
HDTVC
Clock Divide Control (TVC) Hold Time 0.32 0.36 0.43 ns
t
SUSTC
Sample Time Control (STC) Setup Time 1.58 1.79 2.11 ns
t
HDSTC
Sample Time Control (STC) Hold Time 1.27 1.45 1.71 ns
t
SUVAREFSEL
Voltage Reference Select (VAREFSEL) Setup Time 0.00 0.00 0.00 ns
t
HDVAREFSEL
Voltage Reference Select (VAREFSEL) Hold Time 0.67 0.76 0.89 ns
t
SUCHNUM
Channel Select (CHNUMBER) Setup Time 0.90 1.03 1.21 ns
t
HDCHNUM
Channel Select (CHNUMBER) Hold Time 0.00 0.00 0.00 ns
t
SUADCSTART
Start of Conversion (ADCSTART) Setup Time 0.75 0.85 1.00 ns
t
HDADCSTART
Start of Conversion (ADCSTART) Hold Time 0.43 0.49 0.57 ns
t
CK2QBUSY
Busy Clock-to-Q 1.33 1.51 1.78 ns
t
CK2QCAL
Power-Up Calibration Clock-to-Q 0.63 0.71 0.84 ns
t
CK2QVAL
Valid Conversion Result Clock-to-Q 3.12 3.55 4.17 ns
t
CK2QSAMPLE
Sample Clock-to-Q 0.22 0.25 0.30 ns
t
CK2QRESULT
Conversion Result Clock-to-Q 2.53 2.89 3.39 ns
t
CLR2QBUSY
Busy Clear-to-Q 2.06 2.35 2.76 ns
t
CLR2QCAL
Power-Up Calibration Clear-to-Q 2.15 2.45 2.88 ns
t
CLR2QVAL
Valid Conversion Result Clear-to-Q 2.41 2.74 3.22 ns
t
CLR2QSAMPLE
Sample Clear-to-Q 2.17 2.48 2.91 ns
t
CLR2QRESULT
Conversion result Clear-to-Q 2.25 2.56 3.01 ns
t
RECCLR
Recovery Time of Clear 0.00 0.00 0.00 ns
t
REMCLR
Removal Time of Clear 0.63 0.72 0.84 ns
t
MPWSYSCLK
Clock Minimum Pulse Width for the ADC 4.00 4.00 4.00 ns
t
FMAXSYSCLK
Clock Maximum Frequency for the ADC 100.00 100.00 100.00 MHz