Fusion Family of Mixed Signal FPGAs
Revision 4 2-113
(conversion that starts before a previously started conversion is finished). The total time for
calibration still remains 3,840 ADCCLK cycles.
ADC Example
This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode
for a system that runs at 66 MHz. Assume the acquisition times defined in Table 2-44 on page 2-111 for
10-bit mode, which gives 0.549 µs as a minimum hold time.
The period of SYSCLK: t
SYSCLK
= 1/66 MHz = 0.015 µs
Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK
requirement. A higher TVC leads to a higher ADCCLK period.
The minimum TVC is chosen so that t
distrib
and t
post-cal
can be run faster. The period of ADCCLK with a
TVC of 1 can be computed by EQ 24.
EQ 24
The STC value can now be computed by using the minimum sample/hold time from Table 2-44 on
page 2-111, as shown in EQ 25.
EQ 25
You must round up to 3 to accommodate the minimum sample time requirement. The actual sample time,
t
sample
, with an STC of 3, is now equal to 0.6 µs, as shown in EQ 26
EQ 26
Microsemi recommends post-calibration for temperature drift over time, so post-calibration is enabled.
The post-calibration time, t
post-cal
, can be computed by EQ 27. The post-calibration time is 0.24 µs.
EQ 27
The distribution time, t
distrib
, is equal to 1.2 µs and can be computed as shown in EQ 28 (N is number of
bits, referring back to EQ 8 on page 2-97).
EQ 28
The total conversion time can now be summated, as shown in EQ 29 (referring to EQ 23 on page 2-112).
t
sync_read
+ t
sample
+ t
distrib
+ t
post-cal
+
tsync_write
= (0.015 + 0.60 + 1.2 + 0.24 + 0.015) µs = 2.07 µs
EQ 29
The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is shown in
Table 2-47:
Table 2-47 • Optimal Setting at 66 MHz in 10-Bit Mode
TVC[7:0] = 1 = 0x01
STC[7:0] = 3 = 0x03
MODE[3:0] = b'0100 = 0x4*
Note: No power-down after every conversion is chosen in this case; however, if the application is
power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any
performance.
t
ADCCLK
41TVC+ t
SYSCLK
411+ 0.015 µs 0.12 µs===
STC
t
sample
t
ADCCLK
--------------------
2–
0.549 µs
0.12 µs
---------------------- -
2– 4.575 2– 2.575== ==
t
sample
2STC+t
ADCCLK
23+t
ADCCLK
5 0.12 µs 0.6 µs====
t
post-cal
2t
ADCCLK
0.24 µs==
t
distrib
Nt
ADCCLK
10 0.12 1.2 µs===
