• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • AFS1500-2FGG256PP PDF文件及第117页内容在线浏览

AFS1500-2FGG256PP

AFS1500-2FGG256PP首页预览图
型号: AFS1500-2FGG256PP
PDF文件:
  • AFS1500-2FGG256PP PDF文件
  • AFS1500-2FGG256PP PDF在线浏览
功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AFS1500-2FGG256PP
PDF页面索引
[1] 页[2] 页[3] 页[4] 页[5] 页[6] 页[7] 页[8] 页[9] 页[10] 页[11] 页[12] 页[13] 页[14] 页[15] 页[16] 页[17] 页[18] 页[19] 页[20] 页[21] 页[22] 页[23] 页[24] 页[25] 页[26] 页[27] 页[28] 页[29] 页[30] 页[31] 页[32] 页[33] 页[34] 页[35] 页[36] 页[37] 页[38] 页[39] 页[40] 页[41] 页[42] 页[43] 页[44] 页[45] 页[46] 页[47] 页[48] 页[49] 页[50] 页[51] 页[52] 页[53] 页[54] 页[55] 页[56] 页[57] 页[58] 页[59] 页[60] 页[61] 页[62] 页[63] 页[64] 页[65] 页[66] 页[67] 页[68] 页[69] 页[70] 页[71] 页[72] 页[73] 页[74] 页[75] 页[76] 页[77] 页[78] 页[79] 页[80] 页[81] 页[82] 页[83] 页[84] 页[85] 页[86] 页[87] 页[88] 页[89] 页[90] 页[91] 页[92] 页[93] 页[94] 页[95] 页[96] 页[97] 页[98] 页[99] 页[100] 页[101] 页[102] 页[103] 页[104] 页[105] 页[106] 页[107] 页[108] 页[109] 页[110] 页[111] 页[112] 页[113] 页[114] 页[115] 页[116] 页[117] 页[118] 页[119] 页[120] 页[121] 页[122] 页[123] 页[124] 页[125] 页[126] 页[127] 页[128] 页[129] 页[130] 页[131] 页[132] 页[133] 页[134] 页[135] 页[136] 页[137] 页[138] 页[139] 页[140] 页[141] 页[142] 页[143] 页[144] 页[145] 页[146] 页[147] 页[148] 页[149] 页[150] 页[151] 页[152] 页[153] 页[154] 页[155] 页[156] 页[157] 页[158] 页[159] 页[160] 页[161] 页[162] 页[163] 页[164] 页[165] 页[166] 页[167] 页[168] 页[169] 页[170] 页[171] 页[172] 页[173] 页[174] 页[175] 页[176] 页[177] 页[178] 页[179] 页[180] 页[181] 页[182] 页[183] 页[184] 页[185] 页[186] 页[187] 页[188] 页[189] 页[190] 页[191] 页[192] 页[193] 页[194] 页[195] 页[196] 页[197] 页[198] 页[199] 页[200] 页[201] 页[202] 页[203] 页[204] 页[205] 页[206] 页[207] 页[208] 页[209] 页[210] 页[211] 页[212] 页[213] 页[214] 页[215] 页[216] 页[217] 页[218] 页[219] 页[220] 页[221] 页[222] 页[223] 页[224] 页[225] 页[226] 页[227] 页[228] 页[229] 页[230] 页[231] 页[232] 页[233] 页[234] 页[235] 页[236] 页[237] 页[238] 页[239] 页[240] 页[241] 页[242] 页[243] 页[244] 页[245] 页[246] 页[247] 页[248] 页[249] 页[250] 页[251] 页[252] 页[253] 页[254] 页[255] 页[256] 页[257] 页[258] 页[259] 页[260] 页[261] 页[262] 页[263] 页[264] 页[265] 页[266] 页[267] 页[268] 页[269] 页[270] 页[271] 页[272] 页[273] 页[274] 页[275] 页[276] 页[277] 页[278] 页[279] 页[280] 页[281] 页[282] 页[283] 页[284] 页[285] 页[286] 页[287] 页[288] 页[289] 页[290] 页[291] 页[292] 页[293] 页[294] 页[295] 页[296] 页[297] 页[298] 页[299] 页[300] 页[301] 页[302] 页[303] 页[304] 页[305] 页[306] 页[307] 页[308] 页[309] 页[310] 页[311] 页[312] 页[313] 页[314] 页[315] 页[316] 页[317] 页[318] 页[319] 页[320] 页[321] 页[322] 页[323] 页[324] 页[325] 页[326] 页[327] 页[328] 页[329] 页[330] 页[331] 页[332] 页[333] 页[334] 页
120%
Fusion Family of Mixed Signal FPGAs
Revision 4 2-101
There are several popular ADC architectures, each with advantages and limitations. The analog-to-digital
converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It
supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per
second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external
reference voltage can be used.
As shown in Figure 2-81, a SAR ADC contains N capacitors with binary-weighted values.
To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the
capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very
close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the
comparator. Now the conversion process begins. First, C is switched to VREF
.
Because of the binary
weighting of the capacitors, the voltage at the input of the comparator is then shown by EQ 11.
Voltage at input of comparator = –VIN + VREF / 2
EQ 11
If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0.
A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched
back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at
the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the
MSB), and the comparator output now indicates the value of the next most significant bit. This bit is
likewise registered, and the process continues for each subsequent bit until a conversion is completed.
The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.
Figure 2-81 • Example SAR ADC Architecture
Comparator
C C / 2 C / 4
C / 2
N–2
C / 2
N–1
VREF
VIN
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价