Fusion Family of Mixed Signal FPGAs
Revision 4 2-99
Analog-to-Digital Converter Block
At the heart of the Fusion analog system is a programmable Successive Approximation Register (SAR)
ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve
500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input
multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown
in Figure 2-79. The ADC offers multiple self-calibrating modes to ensure consistent high performance
both at power-up and during runtime.
Figure 2-79 • ADC Block Diagram
ADC
12
Analog MUX
(32 to 1)
Temperature
Monitor
Pads
Internal Diode
Digital Output to FPGA
AV0
AC0
AG0
AT0
AV1
AC1
AG1
AT1
AV2
AC2
AG2
AT2
AV3
AC3
AG3
AT3
AV4
AC4
AG4
AT4
AV5
AC5
AG5
AT5
AV6
AC6
AG6
AT6
AV7
AC7
AG7
AT7
AV8
AC8
AG8
AT8
AV9
AC9
AG9
AT9
ATRETURN89
ATRETURN67
ATRETURN45
ATRETURN23
ATRETURN01
Analog
Quad 0
Analog
Quad 4
Analog
Quad 5
Analog
Quad 6
Analog
Quad 7
Analog
Quad 8
Analog
Quad 9
Analog
Quad 3
Analog
Quad 2
Analog
Quad 1
V
CC
(1.5 V)
0
1
31
These are hardwired
connections within
Analog Quad.
CHNUMBER[4:0]
