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AFS1500-2FGG256PP

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型号: AFS1500-2FGG256PP
PDF文件:
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功能描述: Fusion Family of Mixed Signal FPGAs
PDF文件大小: 18780.44 Kbytes
PDF页数: 共334页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
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100%
January 2013 I
© 2013 Microsemi Corporation
Fusion Family of Mixed Signal FPGAs
Features and Benefits
High-Performance Reprogrammable Flash Technology
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Instant On Single-Chip Solution
350 MHz System Performance
Embedded Flash Memory
User Flash Memory – 2 Mbits to 8 Mbits
Configurable 8-, 16-, or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
1 Kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
Up to 12-Bit Resolution and up to 600 Ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
P- and N-Channel Power MOSFET Support
Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
ADC Accuracy is Better than 1%
On-Chip Clocking Support
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 KHz to 20 MHz)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Low Power Consumption
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low-Power Modes
In-System Programming (ISP) and Security
ISP with 128-Bit AES via JTAG
FlashLock
®
Designed to Protect FPGA Contents
Advanced Digital I/O
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS
Built-In I/O Registers
700 Mbps DDR Operation
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
Pin-Compatible Packages across the Fusion
®
Family
SRAMs and FIFOs
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
Soft ARM Cortex-M1 Fusion Devices (M1)
•ARM
®
Cortex-™M1–Enabled
Pigeon Point ATCA IP Support (P1)
Targeted to Pigeon Point
®
Board Management Reference
(BMR) Starter Kits
Designed in Partnership with Pigeon Point Systems
ARM Cortex-M1 Enabled
MicroBlade Advanced Mezzanine Card Support (U1)
Targeted to Advanced Mezzanine Card (AdvancedMC™ Designs)
Designed in Partnership with MicroBlade
8051-Based Module Management Controller (MMC)
Table 1 • Fusion Family
Fusion Devices AFS090 AFS250 AFS600 AFS1500
ARM Cortex-M1
*
Devices M1AFS250 M1AFS600 M1AFS1500
Pigeon Point Devices
P1AFS600 P1AFS1500
MicroBlade Devices
U1AFS250 U1AFS600 U1AFS1500
General
Information
System Gates 90,000 250,000 600,000 1,500,000
Tiles (D-flip-flops) 2,304 6,144 13,824 38,400
Secure (AES) ISP Yes Yes Yes Yes
PLLs 1122
Globals 18 18 18 18
Memory
Flash Memory Blocks (2 Mbits) 1 1 2 4
Total Flash Memory Bits 2M 2M 4M 8M
FlashROM Bits 1,024 1,024 1,024 1,024
RAM Blocks (4,608 bits) 6 8 24 60
RAM kbits 27 36 108 270
Analog and I/Os
Analog Quads 5 6 10 10
Analog Input Channels 15 18 30 30
Gate Driver Outputs 5 6 10 10
I/O Banks (+ JTAG) 4 4 5 5
Maximum Digital I/Os 75 114 172 252
Analog I/Os 20 24 40 40
Note: *Refer to the Cortex-M1 product brief for more information.
Revision 4
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