ADV601
–46–
REV. 0
Table XXXIV. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters
Parameter Description Min Max Unit
t
WR_D_WRC
WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK) N/A
1
N/A ns
t
WR_D_PWA
WR Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK) N/A
1
N/A ns
t
WR_D_PWD
WR Signal, Direct Register, Pulse Width Deasserted (at 27 MHz VCLK) 5 N/A ns
t
ADR_D_WRS
ADR Bus, Direct Register, Write Setup 2 N/A ns
t
ADR_D_WRH
ADR Bus, Direct Register, Write Hold 2 N/A ns
t
DATA_D_WRS
DATA Bus, Direct Register, Write Setup –20 N/A ns
t
DATA_D_WRH
DATA Bus, Direct Register, Write Hold 0 N/A ns
t
WR_D_RDT
WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK) 35.6
2
N/A ns
t
ACK_D_WRD
ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK) 8.6 182.1
3, 4
ns
t
ACK_D_WROH
ACK Signal, Direct Register, Write Output Hold 11 N/A ns
NOTES
1
WR input must be asserted (low) until ACK is asserted (low).
2
Minimum t
WR_D_RDT
varies with VCLK according to the formula: t
WR_D_RDT (MIN)
= 0.8 (VCLK Period) +7.4.
3
Maximum t
WR_D_WRD
varies with VCLK according to the formula: t
ACK_D_WRD (MAX)
= 4.3 (VCLK Period) +14.8.
4
During STATS_R deasserted (low) conditions, t
ACK_D_WRD
may be as long as 52 VCLK periods.
VALID
VALID
VALID VALID
(I) ADR, BE, CS
(I) WR
(I) DATA
(O) ACK
(I) RD
t
ADR_D_WRS
t
DATA_D_WRS
t
ACK_D_WROH
t
WR_D_WRC
t
WR_D_PWA
t
WR_D_PWD
t
ADR_D_WRH
t
DATA_D_WRH
t
ACK_D_WRD
t
WR_D_RDT
Figure 38. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing