ADV601
–38–
REV. 0
CCIR-656 Video Format Timing
The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video
mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label CTRL
indicates the VSYNC, HSYNC, and FIELD pins. Also note that for CCIR-656 video mode, the CREF pin is unused.
Table XXIII. CCIR-656 Video—Decode Pixel (YCrCb) Timing Parameters
Parameter Description Min Max Units
t
VDATA_DC_D
VDATA Signals, Decode CCIR656 Mode, Delay N/A 14 ns
t
VDATA_DC_OH
VDATA Signals, Decode CCIR656 Mode, Output Hold 2 N/A ns
t
CTRL_DC_D
CTRL Signals, Decode CCIR656 Mode, Delay N/A 11 ns
t
CTRL_DC_OH
CTRL Signals, Decode CCIR656 Mode, Output Hold 3 N/A ns
(O) CTRL
(O) VCLKO
t
CTRL_DC_OH
(O) VDATA
t
VDATA_DC_OH
t
VDATA_DC_D
VALID
VALID VALID
t
CTRL_DC_D
VALID
VALID VALID
Figure 25. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Timing
Table XXIV. CCIR-656 Video—Encode Pixel (YCrCb) Timing Parameters
Parameter Description Min Max Units
t
VDATA_EC_S
VDATA Bus, Encode CCIR656 Mode, Setup 2 N/A ns
t
VDATA_EC_H
VDATA Bus, Encode CCIR656 Mode, Hold 5 N/A ns
t
CTRL_EC_D
CTRL Signals, Encode CCIR656 Mode, Delay N/A 33 ns
t
CTRL_EC_OH
CTRL Signals, Encode CCIR656 Mode, Output Hold 20 N/A ns
t
VDATA_EC_H
(O) CTRL
(I) VCLK
(I) VDATA
ASSERTED
VALID
ASSERTED
VALID
t
VDATA_EC_S
t
CTRL_EC_D
t
CTRL_EC_OH
Figure 26. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing
(I) VCLK
(O) VCLKO
(VCLK2 = 0)
(I) VCLKO
(VCLK2 = 1)
t
VCLK_CYC
t
VCLKO_D0
t
VCLKO_D1
NOTE:
USE VCLK FOR CLOCKING VIDEO-ENCODE
OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.
DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.
Figure 24. Video Clock Timing
