ADV601
–32–
REV. 0
APPLYING THE ADV601
This section includes the following topics:
• Using the ADV601 in computer applications
• Using the ADV601 in standalone applications
• Configuring the host interface for 8-, 16- or 32-bit data paths
• Connecting the video interface to popular video encoders and
decoders
• Getting the most out of the ADV601
The following Analog Devices products should be considered in
ADV601 designs:
• ADV7175/ADV7176—Digital YUV to analog composite
video encoder
• AD722—Analog RGB to analog composite video encoder
• AD1843—Audio codec with embedded video synchronization
• ADSP-21xx—Family of fixed-point digital signal processors
• AD8xxx—Family of video operational amplifiers
Using the ADV601 in Computer Applications
Many key features of the ADV601 were driven by the demand-
ing cost and performance requirements of computer applica-
tions. The following ADV601 features provide key advantages in
computer applications:
• Host Interface
The 512 double word FIFO provides necessary buffering of
compressed digital video to deal with PCI bus latency.
• Low Cost External DRAM
Unlike many other real-time compression solutions, the
ADV601 does not require expensive external SRAM trans-
form buffers or VRAM frame stores.
A2
A3
D0–D7
D8–D15
D16–D23
D24–D31
A28
A29
A30
A31
DECODE
1
DECODE
2
VCLK
CREF
VSYNC
HSYNC
VDATA [2:9]
LLC
CREF
ODD
HREF
FIELD
XTAL
SAA7110
29.50000MHz PAL
OR
24.54543MHz NTSC
ADR0
ADR1
DQ0–DQ7
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
CS
STATS_R
LCODE
26.80000MHz
XTAL
A0–A8
D0–D15
A0–A8
DQ1–DQ16
NOTE:
DECODE
1
ASSERTS CS
~
ON THE
ADV601 FOR HOST ADDRESSES
0X4000,0000 THROUGH
0X4000,0013
ADV601
HOST BUS
DRAM
(256K X 16-BIT)
COMPOSITE VIDEO INPUT
VCLKO
TOSHIBA TC514265DJ/DZ/DFT-60
NEC uPD424210ALE-60
NEC uPD42S4210ALE-60
HITACHI HM514265CJ-60
ANY DRAM USED WITH THE ADV601
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
FIFO_SRQ
FIFO_STP
FIFO_ERR
VDATA [12:19]
Y[0–7]
UV[7–0]
DECODE
2
IS HOST SPECIFIC
BE0
BE1
BE2
BE3
RD
WR
HIRQ
ACK
RAS
CAS
WE
RAS
CAS
OE
WEL
WEH
RD
WR
VS
Figure 14. A Suggested PC Application Design
Using the ADV601 In Standalone Applications
Figure 15 shows how to connect the ADV601 in noncomputer
based applications. In this case, an ADSP-2105 (low cost DSP)
performs BW calculations and an ASIC controls the ADV601
though the host interface. Because the ADSP-2105 calculates
BW during the vertical retrace period each field, most of the
DSP’s computational bandwidth is available for other functions
such as audio compression or communication. BW software for
the entire family of Analog Devices’ 16-bit DSPs (including the
ADSP-2105) will be available at no cost from Analog Devices.
Figure 16 shows the ADV601 in another noncomputer based
applications. Here, an ADSP-21csp01 provides Host control
and BW calculation services. Note that all control and BW
operations occur over the host interface in this design.
Connecting the ADV601 to Popular Video Decoders and
Encoders
The following circuits are recommendations only. Analog
Devices has not actually built or tested these circuits.
Using the Brooktree Bt819A Video Decoder
Brooktree has three video decoder parts, the 819A, 817A and
815A. Only the 819A has an output FIFO. Because Brooktree
parts must sample at 8xFsc, this FIFO is needed to resynchronize
output data to the ADV601 data rates.
According to the Brooktree data sheet, the Mode B Asynchro-
nous Pixel Interface (API) must be used to give a continuous
stream of active and blanked data as required by the ADV601.
An external circuit is used to generate RDEN (read enable) pin
input for the Bt819A, and the ADV601 VCLKO signal must be
divided by two; either with an external circuit (as shown) or by
setting the VCLK2 bit in the Mode Control register.
