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ADV601

ADV601首页预览图
型号: ADV601
PDF文件:
  • ADV601 PDF文件
  • ADV601 PDF在线浏览
功能描述: Low Cost Multiformat Video Codec
PDF文件大小: 606.16 Kbytes
PDF页数: 共52页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝ADV601
PDF页面索引
120%
ADV601
–26–
REV. 0
DRAM Manager
The DRAM Manager provides a sorting and reordering func-
tion on the sub-band coded data between the Wavelet Kernel
and the Programmable Quantizer. The DRAM manager pro-
vides a pipeline delay stage to the ADV601. This pipeline lets
the ADV601 extract current field image statistics (min/max
pixel values, sum of pixel values, and sum of squares) used in
the calculation of Bin Widths and re-order wavelet transform
data. The use of current field statistics in the Bin Width calcula-
tion results in precise control over the compressed bit rate. The
DRAM manager manages the entire operation and refresh of the
DRAM.
The interface between the ADV601 DRAM manager and
DRAM is designed to be transparent to the user. The ADV601
DRAM pins should be connected to the DRAM as called out in
the Pin Function Descriptions section. The ADV601 requires
one 256K word by 16-bit, 60 ns DRAM. The following is a
selected list of manufacturers and part numbers. All parts can
be used with the ADV601 at all VCLK rates except where
noted. Any DRAM used with the ADV601 must meet the mini-
mum specifications outlined for the Hyper Mode DRAMs listed
in Table XIII. For DRAM Interface pins descriptions, see the
Pin Function Descriptions.
Table XIII. ADV601 Compatible DRAMs
Manufacturer Part Number Notes
Toshiba TC514265DJ/DZ/DFT-60 None
NEC µPD424210ALE-60 None
NEC µPD42S4210ALE-60 CBR Self Refresh
feature of this prod-
uct is not needed by
the ADV601.
Hitachi HM514265CJ-60 None
Compressed Data-Stream Definition
Through its Host Interface the ADV601 outputs (during en-
code) and receives (during decode) compressed digital video
data. This stream of data passing between the ADV601 and the
host is hierarchically structured and broken up into blocks of
data as shown in Figure 12. Table IV shows pseudo code for a
video data transfer that matches the transfer order shown in
Figure 12 and uses the code names shown in Table XVI. The
blocks of data listed in Figure 12 correspond to wavelet com-
pressed sections of each field illustrated in Figure 13 as a modified
Mallat diagram.
(CONTINUOUS STREAM OF FRAMES)
TIME
FRAME (N) FRAME (N + 1) FRAME (N + 2)
FRAME (N + M)
FIELD 2 SEQUENCEFIELD 1 SEQUENCE
FIELD SEQUENCE STRUCTURE
FIRST BLOCK SEQUENCE COMPLETE BLOCK SEQUENCEVERTICAL INTERFACE TIME CODE
START OF FIELD 1 OR 2 CODE
FIRST BLOCK SEQUENCE STRUCTURE
DATA FOR MALLAT BLOCK 6BIN WIDTH QUANTIZER CODESUB-BAND TYPE CODE
COMPLETE BLOCK SEQUENCE ORDER
(STREAM OF MALLAT
BLOCK SEQUENCES)
SEQUENCE FOR MALLAT BLOCK 3SEQUENCE FOR MALLAT BLOCK 20SEQUENCE FOR MALLAT BLOCK 9
COMPLETE BLOCK (INDIVIDUAL) SEQUENCE STRUCTURE
DATA FOR MALLAT BLOCKBIN WIDTH QUANTIZER CODESTART OF BLOCK CODE
Figure 12. Hierarchical Structure of Wavelet Compressed Frame Data (Data Block Order)
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