ADV601
–20–
REV. 0
Host Interface Pins (Continued)
Name Pins I/O Description
FIFO_STP 1 O FIFO Stop. This condition indicates that the host is far ahead of the ADV601’s
compressed data supply or demand requirements. The state of this pin also appears
in the Interrupt Mask/Status register. Use the interrupt mask to assert a Host inter-
rupt (HIRQ pin) based on the state of the FIFO_STP pin. This pin operates as
follows:
• LO No FIFO Stop condition (FIFOSTP bit LO)
• HI FIFO empty (encode) or full (decode) (FIFOSTP bit HI)
STATS_R 1 O Statistics Ready. This pin indicates the Wavelet Statistics (contents of Sum of
Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and
are ready for the Bin Width calculator to read them from the host or DSP interface.
The frequency of this interrupt will be equal to the field rate. The state of this pin
also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert
a Host interrupt (HIRQ pin) based on the state of the STATS_R pin. This pin
operates as follows:
• LO No Statistics Ready condition (STATSR bit LO)
• HI Statistics Ready for BW calculator (STATSR bit HI)
LCODE 1 O Last Compressed Data (for field). This bit indicates the last compressed data word
for field will be retrieved from the FIFO on the next read from the host bus. The
frequency of this interrupt is similar to the field rate, but varies depending on
compression and host response. The state of this pin also appears in the Interrupt
Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)
based on the state of the LCODE pin. This pin operates as follows:
• LO No Last Code condition (LCODE bit LO)
• HI Last data word for field has been read from FIFO (LCODE bit HI)
HIRQ 1 O Host Interrupt Request. This pin indicates an interrupt request to the Host. The
Interrupt Mask/Status register can select conditions for this interrupt based on any
or all of the following: FIFOSTP, FIFOSRQ, FIFOERR, LCODE, STATR or
CCIR656 unrecoverable error. Note that the polarity of the HIRQ pin can be
modified using the Mode Control register.
RESET 1 I ADV601 Chip Reset. Asserting this pin returns all registers to reset state. Note that
the ADV601 must be reset at least once after power-up with this active low signal
input. For more information on reset, see the SWR bit description.
Power Supply Pins
Name Pins I/O Description
GND 28 I Ground
VDD 21 I +5 V DC Digital Power
