ADV601
–11–
REV. 0
[4] FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0 No FIFO Error condition, reset value (FIFO_ERR pin LO)
1 FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
[5] FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:
0 No FIFO Stop condition, reset value (FIFO_STP pin LO)
1 FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
[6] Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in
the data stream. Note that the ADV601 recovers from this condition without host intervention.
0 No memory error condition, reset value
1 Memory error
[7] Reserved (always read/write zero)
[8] Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0 Disable CCIR-656 data error interrupt, reset value
1 Enable interrupt on error in CCIR-656 data
[9] Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0 Disable Statistics Ready interrupt, reset value
1 Enable interrupt on Statistics Ready
[10] Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0 Disable Last Code Read interrupt, reset value
1 Enable interrupt on Last Code Read from FIFO
[11] Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0 Disable FIFO Service Request interrupt, reset value
1 Enable interrupt on FIFO Service Request
[12] Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0 Disable FIFO Stop interrupt, reset value
1 Enable interrupt on FIFO Stop
[13] Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0 Disable FIFO Error interrupt, reset value
1 Enable interrupt on FIFO Error
[14] Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0 Disable memory error interrupt, reset value
1 Enable interrupt on memory error
[15] Reserved (always read/write zero)
Mode Control Register
Indirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0] Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0 CCIR-656
0x2 MLTPX (Philips)
0x3 Philips, reset value
0x8 Gray Scale
[4] VCLK Output Divided by two, VCLK2. This bit controls the following:
0 Do not divide VCLK output (VCLKO = VCLK), reset value
1 Divide VCLK output by two (VCLKO = VCLK/2)
