ADuM2250/ADuM2251
Rev. 0 | Page 10 of 16
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADuM2250/ADuM2251 interface on each side to I
2
C sig-
nals. Internally, the bidirectional I
2
C signals are split into two
unidirectional channels communicating in opposite directions
via dedicated iCoupler isolation channels. One channel of each
pair (the Side 1 input of each I/O pin in
Figure 6) implements
a special input buffer and output driver that can differentiate
between externally generated inputs and its own output signals.
It only transfers externally generated input signals to the
corresponding Side 2 data or clock pin.
Both the Side 1 and the Side 2 I
2
C pins are designed to interface
to an I
2
C bus operating in the 3.0 V to 5.5 V range. A logic low
on either side causes the corresponding I/O pin across the
coupler to be pulled low enough to comply with the logic low
threshold requirements of other I
2
C devices on the bus. Bus
contention and latch-up is avoided by guaranteeing that the
input low threshold at SDA
1
or SCL
1
is at least 50 mV less than
the output low signal at the same pin. This prevents an output
logic low at Side 1 being transmitted back to Side 2 and pulling
down the I
2
C bus by latching the state.
Because the Side 2 logic levels/thresholds and drive capabilities
comply fully with standard I
2
C values, multiple ADuM2250/
ADuM2251 devices connected to a bus by their Side 2 pins
can communicate with each other and with other devices
having I
2
C compatibility as shown in Figure 7. Note the
distinction between I
2
C compatibility and I
2
C compliance.
I
2
C compatibility refers to situations in which the logic levels
or drive capability of a component do not necessarily meet the
requirements of the I
2
C specification but still allow the com-
ponent to communicate with an I
2
C-compliant device. I
2
C
compliance refers to situations in which the logic levels and
drive capability of a component fully meet the requirements
of the I
2
C specification.
Because the Side 1 pin has a modified output level/input thresh-
old, Side 1 of the ADuM2250/ADuM2251 can only communicate
with devices fully compliant with the I
2
C standard. In other
words, Side 2 of the ADuM2250/ADuM2251 is I
2
C-compliant
while Side 1 is only I
2
C-compatible.
The Side 1 I/O pins must not be connected to other I
2
C
buffers that implement a similar scheme of dual I/O threshold
detection. This latch-up prevention scheme is implemented in
several popular I
2
C level shifting and bus extension products
currently available from Analog Devices and other manufac-
turers. Care should be taken to review the data sheet of
potential I
2
C bus buffering products to ensure that only one
buffer on a bus segment implements a dual threshold scheme.
A bus segment is a portion of the I
2
C bus that is isolated from
other portions of the bus by galvanic isolation, bus extenders, or
level shifting buffers.
Tabl e 11 shows how multiple ADuM2250/
ADuM2251 components can coexist on a bus as long as two
Side 1 buffers are not connected to the same bus segment.
Table 11. ADuM225x Buffer Compatibility
Side 1 Side 2
Side 1
No Yes
Side 2
Yes Yes
The output logic low levels are independent of the V
DD1
and
V
DD2
voltages. The input logic low threshold at Side 1 is also
independent of V
DD1
. However, the input logic low threshold at
Side 2 is designed to be at 0.3 V
DD2
, consistent with I
2
C require-
ments. The Side 1 and Side 2 I/O pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
DECODE
ENCODE
ENCODE
DECODE
DECODE
ENCODE
ENCODE
DECODE
GND
1
NC
V
DD1
NC
SDA
1
SCL
1
NC
GND
1
GND
2
NC
V
DD2
NC
SDA
2
SCL
2
NC
GND
2
06670-006
8
7
5
6
4
3
2
1
12
11
13
14
15
16
10
ADuM2250
SYMBO L INDICATES A DUAL THRESHO LD INP UT BUFFE R.
NC = NO CO NNECT
9
Figure 6. ADuM2250 Block Diagram
V
DD1
SDA
1
SCK
1
GND
1
V
DD2
SDA
2
SCK
2
GND
2
8
7
5
6
4
3
2
1
9
12
11
13
14
15
16
10
ADuM2250
06670-007
µCPU
OR
SECONDARY
BUS
SEGMENT
I
2
C BUS
Figure 7. Typical Isolated I
2
C Interface Using ADuM2250
