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ADL5356-EVALZ

ADL5356-EVALZ首页预览图
型号: ADL5356-EVALZ
PDF文件:
  • ADL5356-EVALZ PDF文件
  • ADL5356-EVALZ PDF在线浏览
功能描述: 1200 MHz to 2500 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun
PDF文件大小: 493.08 Kbytes
PDF页数: 共24页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝ADL5356-EVALZ
PDF页面索引
120%
ADL5356
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
7883-002
24
25
26
23
22
21
1
2
3
9
20
27
19
4
5
6
7
8
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
3
3
3
4
3
5
3
6
3
2
3
1
3
0
2
9
2
8
VGS0
VGS1
VGS2
LOSW
PWDN
VPOS
COMM
LOI2
LOI1
MNIN
MNCT
COMM
DVIN
VPOS
COMM
VPOS
COMM
DVCT
V
P
O
S
D
V
G
M
C
O
M
M
D
V
O
P
D
V
O
N
D
V
L
E
V
P
O
S
D
V
L
G
N
C
M
N
O
N
C
O
M
M
M
N
G
M
V
P
O
S
M
N
O
P
M
N
L
E
V
P
O
S
M
N
L
G
N
C
ADL5356
TOP VIEW
(No t t o S cale)
NOTES
1
2
. NC = NO CONNE CT.
. EX P OSED P AD M US T BE CO NNECTED TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16,
21, 30, 36
VPOS Positive Supply Voltage.
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
11 DVGM Diverstiy Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to
VCC using external inductors.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diverstiy Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22 PWDN
Connect to Ground for Normal Operation. Connect pin to 3 V for disable mode when using
VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26 VGS0, VGS1, VGS2 Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON
Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to
VCC using external inductors.
35 MNGM Main Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
Paddle EPAD Exposed pad must be connected to ground.
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