ADIS16375 Data Sheet
Rev. E | Page 6 of 28
TIMING SPECIFICATIONS
T
A
= 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Parameter Description Min
1
Typ Max Unit
f
SCLK
Serial clock 0.01 15 MHz
t
STALL
Stall period between data 2 µs
t
CLS
Serial clock low period 31 ns
t
CHS
Serial clock high period 31 ns
t
CS
Chip select to clock edge 32 ns
t
DAV
DOUT valid after SCLK edge 10 ns
t
DSU
DIN setup time before SCLK rising edge 2 ns
t
DHD
DIN hold time after SCLK rising edge 2 ns
t
DR
, t
DF
DOUT rise/fall times, ≤100 pF loading 3 8 ns
t
DSOE
CS assertion to data out active
0 11 ns
t
HD
SCLK edge to data out invalid 0 ns
t
SFS
Last SCLK edge to
CS deassertion
32 ns
t
DSHI
CS deassertion to data out high impedance
0 9 ns
t
1
Input sync pulse width 5 µs
t
2
Input sync to data-ready output 430 µs
t
3
Input sync period 440 µs
1
Guaranteed by design and characterization but not tested in production.
Timing Diagrams
CS
SCLK
DOUT
DIN
1 2 3 4 5 6 15 16
R/W A5A6 A4 A3 A2
D2
MSB DB14
D1 LSB
DB13 DB12 DB10DB11 DB2 LSBDB1
t
CS
t
SFS
t
DSHI
t
DAV
t
HD
t
CHS
t
CLS
t
DSOE
t
DHD
t
DSU
09389-002
F
igure 2. SPI Timing and Sequence
F
igure 3. Stall Time and Data Rate
t
3
t
2
t
1
SYNC
CLO CK ( CLKI N)
DATA
READY
OUTPUT
REGISTERS
09389-004
DATA VALI D DATA VALI D
F
igure 4. Input Clock Timing Diagram
