Data Sheet ADIS16375
Rev. E | Page 25 of 28
GENERAL-PURPOSE I/O
There are four general-purpose I/O lines: DIO1, DIO2, DIO3, and
DIO4. The FNCIO_CTRL register controls the basic function of
each I/O line, which provides a number of useful functions.
Table 93. FNCIO_CTRL (Page 3, Base Address = 0x06)
Bits Description (Default = 0x000D)
[15:12] Not used
[11] Alarm indicator: 1 = enabled, 0 = disabled
[10] Alarm indicator polarity: 1 = positive, 0 = negative
[9:8]
Alarm indicator line selection:
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
[7] Sync clock input enable: 1 = enabled, 0 = disabled
[6] Sync clock input polarity: 1 = rising edge, 0 = falling edge
[5:4]
Sync clock input line selection:
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
[3] Data-ready enable: 1 = enabled, 0 = disabled
[2] Data-ready polarity: 1 = positive, 0 = negative
[1:0]
Data-ready line selection:
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
Data-Ready Indicator
FNCIO_CTRL[3:0] provide some configuration options for
using one of the DIOx lines as a data-ready indicator signal,
which can drive a processor’s interrupt control line. The factory-
default assigns DIO2 as a positive-polarity, data-ready signal.
Use the following sequence to change this assignment to DIO1
with a negative polarity: turn to Page 3 (DIN = 0x8003) and set
FNCIO_CTRL[3:0] = 1000 (DIN = 0x8608, then DIN = 0x8700).
The timing jitter on the data-ready signal is ±1.4 µs.
Input Sync/Clock Control
FNCIO_CTRL[7:4] provides some configuration options for using
one of the DIOx lines as an input synchronization signal for
sampling inertial sensor data. For example, use the following
sequence to establish DIO4 as a positive-polarity, input clock pin
and keep the factory default setting for the data-ready function:
turn to Page 3 (DIN = 0x8003) and set FNCIO_CTRL[7:4] =
1111 (DIN = 0x86FD, then DIN = 0x8700). Note that this command
also disables the internal sampling clock, and no data sampling
takes place without the input clock signal. When using this mode,
each clock pulse generates four sequential samples at a rate of
9.84 kHz, which are then averaged together. When selecting a
clock input frequency, consider the 330 Hz sensor bandwidth,
because undersampling the sensors can degrade noise and
stability performance.
General-Purpose I/O Control
When FNCIO_CTRL does not configure a DIOx pin, the
GPIO_CTRL provides a control register for general-purpose use
of the pins. GPIO_CTRL[3:0] provides input/output assignment
controls for each line. When the DIOx lines are inputs, monitor
their level by reading GPIO_CTRL[7:4]. When the DIOx lines
are used as outputs, set their level by writing to GPIO_CTRL[7:4].
For example, use the following sequence to set DIO1 and DIO3
as high and low output lines, respectively, and set DIO2 and
DIO4 as input lines. Turn to Page 3 (DIN = 0x8003) and set
GPIO_CTRL[7:0] = 0x15 (DIN = 0x8815, then DIN = 0x8900).
Table 94. GPIO_CTRL (Page 3, Base Address = 0x08)
Bits Description (Default = 0x0000)
[15:8] Don’t care
[7] General-Purpose I/O Line 4 (DIO4) data level
[6] General-Purpose I/O Line 3 (DIO3) data level
[5] General-Purpose I/O Line 2 (DIO2) data level
[4] General-Purpose I/O Line 1 (DIO1) data level
[3]
General-Purpose I/O Line 4 (DIO4) direction control
(1 = output, 0 = input)
[2]
General-Purpose I/O Line 3 (DIO3) direction control
(1 = output, 0 = input)
[1]
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
[0]
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
POWER MANAGEMENT
The SLP_CFG register (see Table 95) provides four different power
management modes for system-level management: power-down,
timed power-down, normal sleep, and timed sleep. The trade-off
between power-down and sleep mode is between idle power and
recovery time. Power-down mode offers the best idle power
consumption but requires the most time to recover. All volatile
settings are lost during power-down but are preserved during
sleep mode.
For timed sleep mode, turn to Page 3 (DIN = 0x8003), write the
amount of sleep time to SLP_CFG[7:0], and set SLP_CFG[8] = 1
(DIN = 0x9101) to start the sleep period. For a timed power-down
period, change the last command to set SLP_CFG[9] = 1 (DIN =
0x9102). To power down or sleep for an indefinite period, set
SLP_CFG[7:0] = 0x00 first, then set either SLP_CFG[8] or
SLP_CFG[9] to 1. Note that the command takes effect when
the
CS
line goes high. To awaken the device from sleep or power-
down mode, use one of the following options to restore normal
operation:
• Assert
CS
from high to low
• Pulse
RST
low, then high again
• Cycle the power
For example, set SLP_CFG[7:0] = 0x64 (DIN = 0x9064), then
set SLP_CFG[8] = 1 (DIN = 0x9101) to start a sleep period of
100 seconds.
Table 95. SLP_CFG (Page 3, Base Address = 0x10)
Bits Description
[15:10] Not used
[9] Power-down mode
[8] Normal sleep mode
[7:0]
Programmable sleep time bits; 1 sec/LSB;
0x00 = indefinite
If the sleep mode and power-down mode bits are both set high,
then the sleep mode (SLP_CFG[8]) bit take precedence.