Data Sheet ADIS16375
Rev. E | Page 11 of 28
SPI COMMUNICATION
The SPI port supports full duplex communication, as shown in
Figure 15, which enables external processors to write to DIN
while reading DOUT, if the previous command was a read
request. Figure 15 provides a guideline for the bit coding on
both DIN and DOUT.
DEVICE CONFIGURATION
The SPI provides write access to the control registers, one byte at
a time, using the bit assignments shown in Figure 15. Each register
has 16 bits, where Bits[7:0] represent the lower address (listed in
Table 9) and Bits[15:8] represent the upper address. Write to the
lower byte of a register first, followed by a write to its upper byte
second. The only register that changes with a single write to its
lower byte is the PAGE_ID register. For a write command, the
first bit in the DIN sequence is set to 1. The Address Bits[A6:A0]
represent the target address and the Data Command Bits[DC7:DC0]
represent the data being written to the location. Figure 11
provides an example of writing 0x03 to Address 0x00
(PAGE_ID[7:0]), using DIN = 0x8003. This write command
activates the control page for SPI access.
09389-012
SCLK
CS
DIN
DIN = 1000 0000 0000 0011 = 0x8003, W RIT E S 0x03 TO ADDRE S S 0x00
Figure 11. SPI Sequence for Activating the Control Page (DIN = 0x8003)
Dual Memory Structure
Writing configuration data to a control register updates its SRAM
contents, which are volatile. After optimizing each relevant control
register setting in a system, use the manual flash update command,
which is located in GLOB_CMD[3] on Page 3 of the register map.
Activate the manual flash update command by turning to Page 3
(DIN = 0x8003) and setting GLOB_CMD[3] = 1 (DIN = 0x8204,
then DIN = 0x8300). Make sure that the power supply is within
specification for the entire 375 ms processing time for a flash
memory update. Table 9 provides a memory map for all of the
user registers, which includes a column for the flash backup
support associated with each register. A yes in this column
indicates that a register has a mirror location in flash and, when
backed up properly, automatically restores itself during startup
or after a reset. Figure 12 provides a diagram of the dual
memory structure used to manage operation and store critical
user settings.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
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Figure 12. SRAM and Flash Memory Diagram
READING SENSOR DATA
The ADIS16375 automatically starts up and activates Page 0 for
data register access. Write 0x00 to the PAGE_ID register (DIN =
0x8000) to activate Page 0 for data access after accessing any other
page. A single register read requires two 16-bit SPI cycles. The first
cycle requests the contents of a register using the bit assignments in
Figure 15, and then the register contents flow out of DOUT during
the second sequence. The first bit in a DIN command is zero,
followed by either the upper or lower address for the register.
The last eight bits are don’t care, but the SPI requires the full set
of 16 SCLKs to receive the request. Figure 13 includes two register
reads in succession, which starts with DIN = 0x1A00 to request
the contents of the Z_GYRO_OUT register and follows with
0x1800 to request the contents of the Z_GYRO_LOW register.
DIN
DOUT
0x1A00
0x1800
NEXT
ADDRESS
Z_GYRO_OUT
Z_GYRO_LOW
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Figure 13. SPI Read Example
Figure 14 provides an example of the four SPI signals when reading
PROD_ID in a repeating pattern. This is a good pattern to use
for troubleshooting the SPI interface setup and communications
because the contents of PROD_ID are predefined and stable.
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SCLK
CS
DIN
DOUT
DOUT = 0011 1111 1111 0111 = 0x3FF 7 = 16,375 (P ROD_I D)
DIN = 0111 1110 0000 0000 = 0x7E 00
Figure 14. SPI Read Example, Second 16-Bit Sequence
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R/W
R/W
A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
CS
SCLK
DIN
DOUT
A6 A5
D13D14D15
NOTES
1. DOUT BIT S ARE P RODUCED ONL Y WHEN THE P RE V IO US 16- BIT DIN SE QUENCE S TARTS WI TH R/ W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FO R OT HE R DE V ICES .
Figure 15. SPI Communication Bit Sequence
