ADIS16375 Data Sheet
Rev. E | Page 10 of 28
BASIC OPERATION
The ADIS16375 is an autonomous sensor system that starts up
on its own when it has a valid power supply. After running through
its initialization process, it begins sampling, processing, and
loading calibrated sensor data into the output registers, which
are accessible using the SPI port. The SPI port typically connects to
a compatible port on an embedded processor, using the connection
diagram in Figure 9. The four SPI signals facilitate synchronous,
serial data communication. Connect
RST
(see Table 5) to a digital
I/O line for remote reset control or leave it open for normal
operation. The factory default configuration provides users
with a data-ready signal on the DIO2 pin, which pulses high
when new data is available in the output data registers.
SYSTEM
PROCESSOR
SPI MASTER
SCLK
CS
DIN
DOUT
SCLK
SS
MOSI
MISO
+3.3V
IRQ DIO2
VDD
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
10
6
3
5
4
9
11 12
23
13 14 15
ADIS16375
09389-010
F
igure 9. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Mnemonic Function
SS
Slave select
IRQ Interrupt request
MOSI Master output, slave input
MISO Master input, slave output
SCLK Serial clock
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices,
such as the ADIS16375. Table 7 provides a list of settings, which
describe the SPI protocol of the ADIS16375. The initialization
routine of the master processor typically establishes these settings
using firmware commands to write them into its serial control
registers.
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master The ADIS16375 operates as a slave.
SCLK ≤ 15 MHz Maximum serial clock rate.
SPI Mode 3 CPOL = 1 (polarity), and CPHA = 1 (phase).
MSB-First Mode Bit sequence.
16-Bit Mode Shift register/data length.
REGISTER STRUCTURE
The register structure and SPI port provide a bridge between
the sensor processing system and an external, master processor.
It contains both output data and control registers. The output
data registers include the latest sensor data, a real-time clock, error
flags, alarm flags, and identification data. The control registers
include sample rate, filtering, input/output, alarms, calibration,
and diagnostic configuration options. All communication
between the ADIS16375 and an external processor involves
either reading or writing to one of the user registers.
09389-011
TRIAXIS
GYRO
TEMP
SENSOR
DSP
OUTPUT
REGISTERS
CONTROL
REGISTERS
CONTROLLER
TRIAXIS
ACCEL
SPI
F
igure 10. Basic Operation
The register structure uses a paged addressing scheme that is
comprised of 13 pages, with each one containing 64 register
locations. Each register is 16-bits wide, with each byte having its
own unique address within that page’s memory map. The SPI
port has access to one page at a time, using the bit sequences in
Figure 15. Select the page to activate for SPI access by writing its
code to the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Table 8 displays the
PAGE_ID contents for each page, along with their basic function.
The PAGE_ID register is located at Address 0x00 on every page.
Table 8. User Register Page Assignments
Page PAGE_ID Function
0 0x00 Output data, clock, identification
1 0x01 Reserved
2 0x02 Calibration
3 0x03 Control: sample rate, filtering, I/O, alarms
4 0x04 Reserved
5 0x05 FIR Filter Bank A Coefficients, 1 to 60
6 0x06 FIR Filter Bank A, Coefficients, 61 to 120
7 0x07 FIR Filter Bank B, Coefficients, 1 to 60
8 0x08 FIR Filter Bank B, Coefficients, 61 to 120
9 0x09 FIR Filter Bank C, Coefficients, 1 to 60
10 0x0A FIR Filter Bank C, Coefficients, 61 to 120
11 0x0B FIR Filter Bank D, Coefficients, 1 to 60
12 0x0C FIR Filter Bank D, Coefficients, 61 to 120
