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ADC121S625CIMMX

ADC121S625CIMMX首页预览图
型号: ADC121S625CIMMX
PDF文件:
  • ADC121S625CIMMX PDF文件
  • ADC121S625CIMMX PDF在线浏览
功能描述: 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter
PDF文件大小: 1049.98 Kbytes
PDF页数: 共20页
制造商: NSC[National Semiconductor]
制造商LOGO: NSC[National Semiconductor] LOGO
制造商网址: http://www.national.com
捡单宝ADC121S625CIMMX
PDF页面索引
120%
Applications Information (Continued)
4.0 POWER CONSUMPTION
The architecture, design and fabrication process allows the
ADC121S625 to operate at conversion rates up to 200ksps
while requiring very little power. In order to minimize power
consumption in applications requiring sample rates below
50ksps, the ADC121S625 should be run at a f
SCLK
of 3.2
MHz and with the CS rate as slow as the system requires.
The ADC will go into the power down mode at the end of
each conversion, minimizing power consumption. See Sec-
tion 4.2 for more information.
However, some things should be kept in mind to absolutely
minimize power consumption.
The consumption scales directly with conversion rate, so
minimizing power consumption requires determining the low-
est conversion rate that will satisfy the requirements of the
system.
The ADC121S625 goes into its power down mode on the
rising edge of CS or the 14th or 16th falling edge of SCLK
after the fall of CS, as described in the Functional Descrip-
tion, whichever occurs first (see Timing Diagrams). Ideally,
each conversion should occur as quickly as possible, pref-
erably at the maximum rated clock rate and the CS rate used
to determine the sample rate. This causes the converter to
spend the longest possible time in the power down mode.
This is very important for minimizing power consumption as
the converter uses current for the analog circuitry, which
continuously consumes power when converting. So, if less
than 12 bits are needed, power may be saved by bringing
CS high after clocking out the number of bits needed.
Of course, the converter also uses power on each SCLK
transition, as is typical for digital CMOS components, so
stopping the clock when in the power down mode will further
reduce power consumption. As mentioned in the Reference
Input Section 1.0, power consumption is also slightly lower
with lower reference voltages.
There is an important difference between entering the power
down mode after a conversion is complete and CS if left
LOW and the full power down mode when CS is HIGH. Both
of these power down the analog portion of the ADC121S625,
but the digital portion is powered down only when CS is
HIGH. So, if CS is left LOW at the end of a conversion and
the converter is continually clocked, the power consumption
will not be as low as when CS is HIGH.
4.1 Short Cycling
Another way of saving power is to short cycle the conversion
process. This is done by pulling the CS line high after the last
required bit is received from the ADC121S625 output. This is
possible because the ADC121S625 places the latest data bit
on the D
OUT
line as it is generated. If only 8-bits of the
conversion result are needed, for example, the conversion
can be terminated by pulling CS HIGH after the 8th bit has
been clocked out. Halting conversion after the last needed
bit is received is called short cycling.
Short cycling can be used to lower the power consumption in
those applications that do not need a full 12-bit resolution, or
where an analog signal is being monitored until some con-
dition occurs. For example, it may not be necessary to use
the full 12-bit resolution of the ADC121S625 as long as the
signal being monitored is within certain limits. The conver-
sion, then, can be terminated after the first few bits (as low
as 3 or 4 bits, in some cases). This can lower power con-
sumption in both the converter and the rest of the system,
because they spend more time in the power down mode and
less time in the active mode.
Short cycling can also be used to reduce the required num-
ber of SCLK cycles from 16 to 14, allowing for a little faster
throughput. That is, SCLK can be raised after the rise of the
14th SCLK, reducing the overall cycle time (t
CYC
) by about
12%.
4.2 Burst Mode Operation
Normal operation requires the SCLK frequency to be 16
times the sample rate and the CS rate to be the same as the
sample rate. However, because starting a new conversion
requires a new fall of CS, it is possible to have the SCLK rate
much higher than 16 times the CS rate. When this is done,
the device is said to be operating in the Burst Mode.
Burst Mode operation has the advantage of lowering overall
power consumption because the device goes into power
down when conversion is complete and only the output
register and output drivers remain powered up to clock out
the data. This circuit also powers down and the output
drivers go into their high impedance state once the last bit is
clocked out.
Note that the output register and output drivers will remain
powered up longer if CS is not brought high before the 15th
fall of SCLK after the fall of CS. See the Double Cycle Timing
Diagram.
5.0 TIMING CONSIDERATIONS
Proper operation requires that the fall of CS occur between
the fall and rise of SCLK. If the fall of CS occurs while SCLK
is high, the data might be clocked out one bit early. Whether
or not the data is clocked out early depends upon how close
the CS transition is to the SCLK transition, the device tem-
perature, and characteristics of the individual device. To
ensure that the data is always clocked out at a time, it is
essential that the fall of CS always occurs while SCLK is low.
6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS
Care should be taken with the physical layout of the printed
circuit board so that best performance may be realized. This
is especially true with a low reference voltage or when the
conversion rate is high. At high clock rates there is less time
for settling, so it is important that any noise settles out much
faster if accuracy is to be maintained.
Any SAR architecture is sensitive to spikes on the power
supply, reference, and ground connections that occur just
prior to latching the comparator output. Spikes might origi-
nate, for example, from switching power supplies, digital
logic, and high power devices, and other sources. This type
of problem can be very difficult to track down if the glitch is
almost synchronous to the converters SCLK, but the phase
difference between SCLK and the noise source may change
with time and temperature, causing sporadic problems.
Power to the ADC121S625 should be clean and well by-
passed. A 0.1µF ceramic bypass capacitor and a 1µF to
10µF capacitor should be used to bypass the ADC121S625
supply, with the 0.1µF capacitor placed as close to the
ADC121S625 package as possible. Adding a 10 resistor in
series with the power supply line will help to low pass filter a
noisy supply.
The reference input should be bypassed with a minimum
0.1µF capacitor. A series resistor and large capacitor can be
used to low pass filter the reference voltage. If the reference
voltage originates from an op-amp, be careful that the op-
amp can drive the bypass capacitor without oscillation (the
ADC121S625
www.national.com17
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