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AD9707BCPZRL7

AD9707BCPZRL7首页预览图
型号: AD9707BCPZRL7
PDF文件:
  • AD9707BCPZRL7 PDF文件
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功能描述: Digital-to-Analog Converters
PDF文件大小: 1259.41 Kbytes
PDF页数: 共42页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝AD9707BCPZRL7
PDF页面索引
120%
AD9704/AD9705/AD9706/AD9707 Data Sheet
Rev. D | Page 38 of 42
0
0 203050709010 40 60 80
I
CLKVDD
(mA)
f
CLOCK
(MSPS)
05926-099
0.2
0.6
0.4
0.8
1.0
1.2
1.4
Figure 85. I
CLKVDD
vs. f
CLOCK
(Differential Clock Mode) at CLKVDD = 1.8 V
Sleep Operation (Pin Mode)
The
AD9704/AD9705/AD9706/AD9707 have a sleep mode that
turns off the output current and reduces the total power consumed
by the device. This mode is activated by applying a Logic 1 to
the SLEEP/CSB pin. The SLEEP/CSB pin logic threshold is
equal to 0.5 × DVDD. This digital input also contains an active
pull-down circuit.
The
AD9704/AD9705/AD9706/AD9707 take less than 50 ns to
power down and approximately 5 μs to power back up, when
3.3 V AVDD is used.
Sleep and Power-Down Operation (SPI Mode)
The
AD9704/AD9705/AD9706/AD9707 offer three power-down
functions that can be controlled through the SPI. These power-
down modes can be used to minimize the power dissipation of
the device. The power-down functions are controlled through
Register 0x00, Bit 1 to Bit 3, of the SPI registers. Table 25
summarizes the power-down functions that can be controlled
through the SPI. The power-down mode can be enabled by
writing a Logic 1 to the corresponding bit in Register 0x00.
Table 25. Power-Down Mode Selection
Power-Down
Mode
(Reg. 0x00)
Bit Number
Functional Description
Clock Off 1 Turn off clock
Sleep 2 Turn off output current
Power Down 3
Turn off output current and
internal band gap reference
SELF-CALIBRATION
The
AD9704/AD9705/AD9706/AD9707 have a self-calibration
feature that improves the DNL of the device. Performing a self-
calibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 1 MHz are generally
influenced more by dynamic device behavior than by DNL, and
in these cases, self-calibration is unlikely to provide any benefits
for single-tones, as shown in Figure 86. Figure 87 shows that
self-calibration is helpful up to 20 MHz for two-tone IMD spaced
10 kHz apart.
88
86
84
82
80
78
00.20.40.60.8
05926-096
SF DR ( dBc)
f
OUT
(MHz)
CALIBRATED
UNCALIBRATED
Figure 86. AD9707 SFDR vs. f
OUT
at 175 MSPS and I
OUTFS
= 2 mA
88
87
86
85
84
83
82
81
80
78
79
0 5 10 15 20
05926-097
IMD (dBc)
LOWER f
OUT
(MHz)
CALIBRATED
UNCALIBRATED
Figure 87. IMD vs. Lower f
OUT
at 175 MSPS and I
OUTFS
= 2 mA
The calibration clock frequency is equal to the DAC clock divided
by the division factor chosen by the DIVSEL value. The frequency
of the calibration clock must be set to under 10 MHz for reliable
calibrations. Best results are obtained by setting DIVSEL[2:0]
(Register 0x0E, Bit 2 to Bit 0) to produce the lowest frequency
calibration clock frequency that the system requirements of the
user allows.
To perform a device self-calibration, use the following procedure:
1. Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
2. Enable self-calibration by writing 0x40 to Register 0x0F.
3. Wait approximately 4500 calibration clock cycles. Each
calibration clock cycle is between 2 DAC clock cycles and
256 DAC clock cycles, depending on the value of
DIVSEL[2:0].
4. Check if the self-calibration has completed by reading the
CALSTAT bit (Register 0x0F, Bit 7). A Logic 1 indicates the
calibration has completed.
5. When the self-calibration has completed, write 0x00 to
Register 0x0F.
6. Disable the calibration clock by clearing the CALCLK bit
(Register 0x02, Bit 0).
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