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AD9707BCPZRL7

AD9707BCPZRL7首页预览图
型号: AD9707BCPZRL7
PDF文件:
  • AD9707BCPZRL7 PDF文件
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功能描述: Digital-to-Analog Converters
PDF文件大小: 1259.41 Kbytes
PDF页数: 共42页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝AD9707BCPZRL7
PDF页面索引
120%
AD9704/AD9705/AD9706/AD9707 Data Sheet
Rev. D | Page 12 of 42
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9707
DB1
DB2
DB3
DB4
DB5
DVDD
DB6
DB7
PIN/SPI/RESET
AVDD
OTCM
IOUTB
IOUTA
ACOM
REFIO
FS ADJ
MODE/SDIO
CMODE/SCLK
CLKVDD
CLKCOM
CLK–
CLK+
DCOM
DB0 (LSB)
SLEEP/CSB
DCOM
DB13 (MSB)
DB12
DB11
DB10
DB9
DB8
05926-003
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER GROUND
PLANE FOR ENHANCED ELECTRICAL AND THERMAL
PERFORMANCE.
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9707
TOP VIEW
(Not to Scale)
Figure 3.
AD9707 Pin Configuration
Table 9. AD9707 Pin Function Descriptions
Pin No. Mnemonic Description
28 to 32, 1,
2, 4 to 8
DB12 to DB1 Data Bit 12 to Data Bit 1.
3 DVDD Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
9 DB0 (LSB) Least Significant Data Bit (LSB).
10, 26 DCOM Digital Common.
11 CLKVDD Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
12 CLK+ Positive Differential Clock Input.
13 CLK− Negative Differential Clock Input.
14 CLKCOM Clock Common.
15 CMODE/SCLK
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial
data clock input.
16 MODE/SDIO
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos
complement. In SPI mode, this pin acts as SPI data input/output.
17 PIN/SPI/RESET
Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
18 AVDD Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
19 OTCM Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
20 IOUTB Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
21 IOUTA DAC Current Output. Full-scale current is sourced when all data bits are 1s.
22 ACOM Analog Common.
23 REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V
reference output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal
reference is activated.
24 FS ADJ Full-Scale Current Output Adjust.
25 SLEEP/CSB In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).
27 DB13 (MSB) Most Significant Data Bit (MSB).
EPAD
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced
electrical and thermal performance.
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