AD8422 Data Sheet
R
G
Power Dissipation
The AD8422 duplicates the differential voltage across its inputs
onto the R
G
resistor. Choose an R
G
resistor size that is sufficient
to handle the expected power dissipation at ambient temperature.
REFERENCE TERMINAL
The output voltage of the AD8422 is developed with respect to the
potential on the reference terminal. This can be used to apply a
precise offset to the output signal. For example, a voltage source
can be tied to the REF pin to level shift the output, allowing the
AD8422 to drive a unipolar analog-to-digital converter (ADC).
The REF pin is protected with ESD diodes and must not exceed
either +V
S
or −V
S
by more than 0.3 V.
For best performance, maintain a source impedance to the REF
terminal that is below 1 Ω. As shown in Figure 55, the reference
terminal, REF, is at one end of a 10 kΩ resistor. Additional
impedance at the REF terminal adds to this 10 kΩ resistor and
results in amplification of the signal connected to the positive input.
The amplification from the additional R
REF
can be calculated as
2(10 kΩ + R
REF
)/(20 kΩ + R
REF
)
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades CMRR.
INCORRECT
V
CORRECT
AD8422
OP1177
+
–
V
REF
AD8422
REF
11197-059
Figure 56. Driving the Reference Pin (REF)
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8422 applies gain in the
first stage before removing common-mode voltage with the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 55) experience a
combination of a gained signal, a common-mode signal, and a
diode drop. The voltage supplies can limit the combined signal,
even when the individual input and output signals are not limited.
Figure 10 through Figure 13 show this limitation in detail.
LAYOUT
To ensure optimum performance of the AD8422 at the PCB level,
take care in the design of the board layout. To aid in this task,
the pins of the AD8422 are arranged in a logical manner.
TOP VIEW
(No t t o Scal e)
11197-060
–IN
1
R
G
2
R
G
3
+IN
4
+V
S
8
V
OUT
7
REF
6
–V
S
5
AD8422
Figure 57. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To maintain high
CMRR over frequency, closely match the input source imped-
ance and capacitance of each path. Place additional source
resistance in the input path (for example, for input protection)
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins (R
G
) can also affect
CMRR over frequency. If the board design has a component at
the gain setting pins (for example, a switch or jumper), choose a
component such that the parasitic capacitance is as small as
possible.
Power Supplies and Grounding
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance.
Place a 0.1 µF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended. A
parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor. As shown in
Figure 58, a 10 µF capacitor can be used farther away from the
device. For larger value capacitors, intended to be effective at
lower frequencies, the current return path distance is less critical.
In most cases, this capacitor can be shared by other local precision
integrated circuits.
AD8422
+V
S
+IN
–IN
LOAD
R
G
REF
0.1µF
10µF
0.1µF
10µF
–V
S
V
OUT
11197-061
Figure 58. Supply Decoupling, REF, and Output Referred to Local Ground
Rev. A | Page 20 of 24
