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AD7911AUJZ-REEL7

AD7911AUJZ-REEL7首页预览图
型号: AD7911AUJZ-REEL7
PDF文件:
  • AD7911AUJZ-REEL7 PDF文件
  • AD7911AUJZ-REEL7 PDF在线浏览
功能描述: 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
PDF文件大小: 353.33 Kbytes
PDF页数: 共28页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝AD7911AUJZ-REEL7
PDF页面索引
120%
AD7911/AD7921
Rev. A | Page 7 of 28
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
1
10 kHz min
2
5 MHz max
t
CONVERT
16 × t
SCLK
AD7921
14 × t
SCLK
AD7911
t
QUIET
30 ns min Minimum quiet time required between bus relinquish and start of next conversion
t
1
15 ns min
Minimum CS
pulse width
t
2
10 ns min
CS
to SCLK setup time
t
3
3
30 ns max
Delay from CS
until DOUT three-state is disabled
t
4
3
45 ns max DOUT access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
4
10 ns min SCLK to DOUT valid hold time
t
8
5 ns min DIN setup time prior to SCLK falling edge
t
9
6 ns min DIN hold time after SCLK falling edge
t
10
5
30 ns max SCLK falling edge to DOUT three-state
10 ns min
SCLK falling edge to DOUT three-state
t
POWER-UP
6
1 μs max Power-up time from full power-down
1
Mark/space ratio for SCLK input is 40/60 to 60/40.
2
Minimum f
SCLK
at which specifications are guaranteed.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V
IH
or V
IL
voltage.
4
Measured with a 50 pF load capacitor.
5
T
10
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
See the Power-Up Time section.
TIMING DIAGRAMS
04350-0-002
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
04350-0-003
SCLK
V
IH
V
IL
DOUT
t
4
Figure 3. Access Time after SCLK Falling Edge
04350-0-004
SCLK
V
IH
V
IL
DOUT
t
7
Figure 4. Hold Time after SCLK Falling Edge
04350-0-005
SCLK
1.6V
DOUT
t
10
Figure 5. SCLK Falling Edge to DOUT Three-State
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