• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • AD2S80ABD PDF文件及第9页内容在线浏览

AD2S80ABD

AD2S80ABD首页预览图
型号: AD2S80ABD
PDF文件:
  • AD2S80ABD PDF文件
  • AD2S80ABD PDF在线浏览
功能描述: Variable Resolution, Monolithic Resolver-to-Digital Converter
PDF文件大小: 188.29 Kbytes
PDF页数: 共16页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝AD2S80ABD
PDF页面索引
120%
AD2S80A
REV. B
–9–
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic LO to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic HI
state to enable the output latches to be updated.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input
The ENABLE input determines the state of the output data. A
logic HI maintains the output data pins in the high imped-
ance condition, and the application of a logic LO presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least signifi-
cant byte will be presented on data output DB9 to DB16 (with
the ENABLE input taken to a logic LO) regardless of the
state of the BYTE SELECT pin. Note that when the AD2S80A is
used with a resolution less than 16 bits the unused data lines are
pulled to a logic LO. A logic HI on the BYTE SELECT input
will present the eight most significant data bits on data output
DB1 and DB8. A logic LO will present the least significant
byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli-
cate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all 1s to all 0s or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulse width of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next consecutive pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to
prevent false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
IN4148
IN4148
RIPPLE
CLOCK
5V
5k
BUSY
5V
10k
1k
0V
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO."
2N3904
Figure 2. Diode Transistor Logic Nand Gate
DIRECTION Output
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This corresponds to a change in input rotation
direction but less than 1 LSB.
DIGITAL TIMING
t
4
BUSY
RIPPLE
CLOCK
DATA
DIR
DATA
BYTE
SELECT
DATA
INHIBIT
INHIBIT
ENABLE
V
H
V
L
V
H
V
H
V
L
V
H
V
H
V
L
V
L
V
L
V
H
V
L
V
L
V
Z
V
H
V
H
V
L
t
13
t
12
t
10
t
7
t
6
t
2
t
1
t
3
t
5
t
9
t
11
t
8
PARAMETER T
MIN
T
MAX
CONDITION
t
1
200 600 BUSY WIDTH V
H
–V
H
t
2
10 25 RIPPLE CLOCK V
H
TO BUSY V
H
t
3
470 580 RIPPLE CLOCK V
L
TO NEXT BUSY V
H
t
4
16 45 BUSY V
H
TO DATA V
H
t
5
3 25 BUSY V
H
TO DATA V
L
t
6
70 140 INHIBIT V
H
TO BUSY V
H
t
7
485 625 MIN DIR V
H
TO BUSY V
H
t
8
515 670 MIN DIR V
H
TO BUSY V
H
t
9
600 INHIBIT V
L
TO DATA STABLE
t
10
40 110 ENABLE V
L
TO DATA V
H
t
11
35 110 ENABLE V
L
TO DATA V
L
t
12
60 140 BYTE SELECT V
L
TO DATA STABLE
t
13
60 125 BYTE SELECT V
H
TO DATA STABLE
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价