AD1934
Rev. 0 | Page 7 of 28
Parameter Condition Comments Min Max Unit
DAC SERIAL PORT See Figure 16
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup To DBCLK rising, slave mode 10 ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DLS
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
AUXTDM SERIAL PORT See Figure 17
t
ABH
AUXTDMBCLK high Slave mode 10 ns
t
ABL
AUXTDMBCLK low Slave mode 10 ns
t
ALS
AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns
t
ALH
AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns
t
ALS
AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns
t
DDH
DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns
AUXILIARY INTERFACE
t
DXDD
AUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns
