AD1934
Rev. 0 | Page 21 of 28
Table 17. PLL and Clock Control 1
Bit Value Function Description
0 0 PLL clock DAC clock source select
1 MCLK
1 0 PLL clock Clock source select
1 MCLK
2 0 Enabled On-chip voltage reference
1 Disabled
3 0 Not locked PLL lock indicator (read-only)
1 Locked
7:4 0000 Reserved
DAC CONTROL REGISTERS
Table 18. DAC Control 0
Bit Value Function Description
0 0 Normal Power-down
1 Power-down
2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
5:3 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
7:6 00 Stereo (normal) Serial format
01 TDM (daisy chain)
10 DAC aux mode (DAC-, TDM-coupled)
11 Dual-line TDM
Table 19. DAC Control 1
Bit Value Function Description
0 0 Latch in midcycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)
2:1 00 64 (2 channels) BCLKs per frame
01 128 (4 channels)
10 256 (8 channels)
11 512 (16 channels)
3 0 Left low LRCLK polarity
1 Left high
4 0 Slave LRCLK master/slave
1 Master
5 0 Slave BCLK master/slave
1 Master
6 0 DBCLK pin BCLK source
1 Internally generated
7 0 Normal BCLK polarity
1 Inverted
