AD1934
Rev. 0 | Page 18 of 28
DBCLK
DLRCLK
DSDATA
LEFT-JUSTIFIED
MODE
DSDATA
RIGHT-JUSTIFIED
MODE
DSDATA
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB LSB
MSB–1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06106-014
Figure 16. DAC Serial Timing
AUXTDMBCLK
AUXTDMLRCLK
DSDATA1
LEFT-JUSTIFIED
MODE
DSDATA1
RIGHT-JUSTIFIED
MODE
DSDATA1
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ALH
06106-015
Figure 17. AUXTDM Serial Timing
