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AD1934

AD1934首页预览图
型号: AD1934
PDF文件:
  • AD1934 PDF文件
  • AD1934 PDF在线浏览
功能描述: 8-Channel DAC with PLL, 192 kHz, 24 Bits
PDF文件大小: 527.6 Kbytes
PDF页数: 共28页
制造商: AD[Analog Devices]
制造商LOGO: AD[Analog Devices] LOGO
制造商网址: http://www.analog.com
捡单宝AD1934
PDF页面索引
120%
AD1934
Rev. 0 | Page 16 of 28
DAISY-CHAIN MODE
The AD1934 also allows a daisy-chain configuration to expand
the system 16 DACs (see
Figure 12). In this mode, the DBCLK
frequency is 512 f
S
. The first eight slots of the DAC TDM data
stream belong to the first AD1934 in the chain and the last eight
slots belong to the second AD1934. The second AD1934 is the
device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1934 can be configured into a dual-line, DAC TDM mode,
as shown in
Figure 13. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1934 in the chain and the last four channels belong to
the second AD1934.
The dual-line, DAC TDM mode can also be used to send data at
a 192 kHz sample rate into the AD1934, as shown in
Figure 14.
The I/O pins of the serial ports are defined according to the
serial mode selected. See
Table 13 for a detailed description of
the function of each pin. See
Figure 18 for a typical AD1934
configuration with two external stereo DACs.
Figure 15 and
Figure 16 show the serial mode formats. For maximum
flexibility, the polarity of LRCLK and BCLK are programmable.
In these figures, all of the clocks are shown with their normal
polarity. The default mode is I
2
S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1934
DSDATA2 (TDM_OUT)
OF THE SECOND AD1934
THIS IS THE TDM
TO THE FIRST AD1934
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1934
FIRST
AD1934
06106-054
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain)
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2
DSDATA3
(IN)
DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4
DSDATA2
(OUT)
DAC L1 DAC R1 DAC L2 DAC R2
DSDATA4
(OUT)
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1934
FIRST
AD1934
MSB
06106-055
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
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