9 INSTRUCTION SET
Code Instruction
RS
R/
W
D7 D6 D5 D4 D3 D2 D1 D0
Description
E.T.(f
OSC
=270
KHZ)
Clear
Display
0 0 0 0 0 0 0 0 0 1
Write”20H” to DDRAM and set DDRAM
address to “00H” from AC
1.53 ms
Return
Home
0 0 0 0 0 0 0 0 1 --
Sets DD RAM address to “00H” from AC
and return cursor to its original position if
shifted. The contents of DDRAM are not
changed.
1.53 ms
Entry Mode
SET
0 0 0 0 0 0 0 1 I/D SH
Assign cursor moving direction and enable
the shift of entire display.
39 µS
Display
ON/OFF
Control
0 0 0 0 0 0 1 D C B
Set display (D), cursor (C), and blink of
cursor (B) on/off control bit.
39 µS
Cursor or
Display
Shift
0 0 0 0 0 1
S/
C
R/
L
-- --
Set cursor moving and display shift control
bit, and the direction, without changing of
DDRAM data.
39 µS
Function
Set
0 0 0 0 1 DL N F -- --
Sets interface data length (DL:8-bit/4-bit),
number of display lines (N:2-line/1-line)
and , display font type (F:5x11dots/5x8
dost).
39 µS
Set CG
RAM
Address
0 0 0 1
AC
5
AC
4
AC
3
AC
2
AC
1
AC
0
Sets CG RAM address in address counter.
39 µS
Set DD
RAM
Address
0 0 1
AC
6
AC
5
AC
4
AC
3
AC
2
AC
1
AC
0
Sets DD RAM address in address counter.
39 µS
Read Busy
Flag and
Address
0 1 BF
AC
6
AC
5
AC
4
AC
3
AC
2
AC
1
AC
0
Whether during internal operation or not
can be known by reading BF. The contents
of address counter can also be read.
0 µS
Write Data
to RAM
1 0 D7 D6 D5 D4 D3 D2 D1 D0
Writes data into internal RAM (DD RAM
/CG RAM).
43 µS
Read Data
from RAM
1 1 D7 D6 D5 D4 D3 D2 D1 D0
Reads data from internal RAM (DD RAM
/CG RAM).
43 µS
* “--“ : don’t care
Note : When an MPU program with checking the Busy Flag(DB7) is made, it must be
necesssary1/2Fosc is necessary for executing the next instruction by the falling edge of the ‘E’
signal after the Busy Flag(DB7) goes to “LOW”.
Date : 2001/12/12 AMPIRE CO., LTD.
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